Rajeev Balasubramonian

Professor
School of Computing
University of Utah

CV | Detailed research page | Full publication list | Teaching page | Utah Arch Research Group | Blog | YouTube

Research

Recent Activities:

• ACM SIGARCH Blog Editor.
• Book: Innovations in the Memory System.
• HPCA 2019 Program Co-Chair.
• Tutorial on Runtimes in the Cloud, 2018, 2019, 2020.
• IEEE Micro Special Issue on Near Data Processing, guest co-editor, Jan/Feb 2016.
• 3rd Workshop on Near-Data Processing, co-located with MICRO 2015.
• 2nd Workshop on Near-Data Processing, co-located with MICRO 2014.
• The Memory Forum, co-located with ISCA 2014.
• ASPLOS 2014
• 1st Workshop on Near-Data Processing, co-located with MICRO 2013.
• JWAC Memory Scheduling Championship at ISCA 2012, based on the USIMM memory system simulation infrastructure.
• Book: Multi-Core Cache Hierarchies.

Recent Papers (Full list of publications):

• HPCA 2022: CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration.
• MICRO 2021: OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations.
• ISCA 2021: Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication
• ISCA 2020: SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks
• ISCA 2020: Compact Leakage-Free Support for Integrity and Reliability
• MICRO 2019: Wire-Aware Architecture and Dataflow for CNN Accelerators. Lightning talk video
• MICRO 2019: GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. Lightning talk video
• ASPLOS 2019: ρ: Relaxed Hierarchical ORAM. Lightning talk video
• ISPASS 2019: The POP Detector: A Lightweight Online Program Phase Detection Framework.
• IEEE Micro 2018: Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. [Expanded arxiv version]
• ASPLOS 2018: VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures.
• HPCA 2018: Secure DIMM: Moving ORAM Primitives Closer to Memory. Lightning talk video
• ACM TACO 2017: CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.
• IJCNN 2017: INXS: Bridging the Throughput and Energy Gap for Spiking Neural Networks.
• ICCD 2016: Enabling Technologies for Memory Compression: Metadata, Mapping, and Prediction.
• ICCD 2016: Understanding and Alleviating Intra-Die and Intra-DIMM Parameter Variation in the Memory System.
• ISCA 2016: ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. Videos: Part I and Part II. Top Picks Honorable Mention
• IEEE Solid-State Circuits Magazine: Making the Case for Feature-Rich Memory Systems: The March Toward Specialized Systems.
• ISPASS 2016: Addressing Service Interruptions in Memory with Thread-to-Rank Assignment. Best Paper Award
• MICRO 2015: Efficiently Prefetching Complex Address Patterns.
• MICRO 2015: Avoiding Information Leakage in the Memory Controller with Fixed Service Policies.
• ICCD 2015: Improving Memristor Memory with Sneak Current Sharing.
• ICCD 2015: Fixed-Function Hardware Sorting Accelerators for Near Data MapReduce Execution.
• HPCA 2015: Overcoming the Challenges of Crossbar Resistive Memory Architectures.
• SC 2014: Managing DRAM Latency Divergence in Irregular GPGPU Applications.
• IEEE Micro Special Issue on Big Data 2014: Comparing Implementations of Near Data Computing with In-Memory MapReduce Workloads.
• IEEE Micro Special Issue on Big Data 2014: Near-Data Processing: Insight from a Workshop at MICRO-46.
• ISPASS 2014: NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce Workloads.
• HPCA 2014: MemZip: Exploiting Unconventional Benefits from Memory Compression.
• HPCA 2014: Sandbox Prefetching: Safe, Run-Time Evaluation of Aggressive Prefetchers. Top Picks Honorable Mention

Older Selected Publications (Full list of publications) :

• MICRO 2013: Quantifying the Relationship between the Power Delivery Network and Architectural Policies in a 3D-Stacked Memory Device.
• HPCA 2013: A Novel System Architecture for Web Scale Applications Using Lightweight CPUs and Virtualized I/O.
• MICRO 2012: Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.
• ISCA 2012: LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems.
• HPCA 2012: Efficient Scrub Mechanisms for Error-Prone Emerging Memories.
• HPCA 2012: Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads.
• ISCA 2011: Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems.
• TOP PICKS 2011: CHOP: Integrating DRAM Caches for CMP Server Platforms.
• PACT 2010 Best Paper: Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers.
• ISCA 2010: Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores.
• ASPLOS 2010: Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement.
• HPCA 2010: Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks.
• HPCA 2010: CHOP: Adaptive Filter-based DRAM Caching for CMP Server Platforms.
• HPCA 2009: Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches.
• HPCA 2009: Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy.
• TOP PICKS 2008: Architecting Efficient Interconnects for Large Caches with CACTI 6.0.
• MICRO 2007: Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0.
• MICRO 2007: Leveraging 3D Technology for Improved Reliability.
• ISCA 2007: Interconnect Design Considerations for Large NUCA Caches.
• ISCA 2006: Interconnect-Aware Coherence Protocols for Chip Multiprocessors.
• HPCA 2005: Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.

• Accelerators: designing accelerators for machine learning applications, genomic analysis, and security primitives.
• Memory Systems : optimizing DRAM/NVM chips and security for data-intensive workloads.

• Reliability : efficient mechanisms to support chipkill reliability in the memory system.
• Large cache design : methodologies to model large NUCA cache hierarchies, policies to organize data, and organizations in 3D.
• Interconnect design : leveraging different wires in a heterogeneous network for architectural innovation.
• Transactional memory : innovations for scalable hardware transactional memory.

Books

Innovations in the Memory System , Rajeev Balasubramonian, Synthesis Lectures on Computer Architecture , Morgan and Claypool Publishers, 2019.

Multi-Core Cache Hierarchies , Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar, Synthesis Lectures on Computer Architecture , Morgan and Claypool Publishers, 2011.

Software Release

CACTI 7

USIMM

CACTI 6.0 ( CACTI mirror site )

Teaching

In Spring 2022, I am teaching CS 3810 Computer Organization. I also usually teach CS 6810 Computer Architecture. I have previously taught Neuromorphic Architectures (CS 7710), CS 7810 Advanced Computer Architecture, and the Architecture/VLSI Seminar (CS 7937). Courses taught in the past are listed here.

Students

Graduated:

• Naveen Muralimanohar , Ph.D. September 2008, Wire-Aware Cache Architectures , First employment: HP Labs, Current employment: Google.
• Niti Madan , Ph.D. January 2009, Leveraging Mixed-process 3D Die Stacking Technology for Cache Hierarchies and Reliability , First employment: Computing Innovation Fellow at IBM T.J. Watson, Current employment: AMD Research.
• Manu Awasthi , Ph.D. September 2011, Managing Data Locality in Future Memory Hierarchies Using a Hardware Software Co-Design Approach , First employment: Micron, Current employment: Asoka University.
• Aniruddha Udipi , Ph.D. March 2012, Designing Efficient Memory for Future Computing Systems , First employment: ARM, Current employment: Google.
• Kshitij Sudan , Ph.D. October 2012, Data Placement for Efficient Main Memory Access , First employment: Samsung, Current employment: ARM.
• Niladrish Chatterjee , Ph.D. September 2013, Designing Efficient Memory Schedulers for Future Systems , First employment: NVidia.
• Seth Pugsley , Ph.D. May 2014, Opportunities for Near Data Computing in MapReduce Workloads , First employment: Intel.
• Manju Shevgoor , Ph.D. October 2015, Enabling Big Memory with Emerging Technologies, First employment: Intel, Current employment: Apple.
• Ali Shafiee , Ph.D. August 2017, Hardware Accelerators for Deep Learning, First employment: Samsung.
• Karl Taht, Ph.D. April 2020, Introspective Computing, First employment: Facebook.
• Anirban Nag, Ph.D. October 2020, Enabling Near Data Processing for Emerging Workloads, First employment: Uppsala University.
• Meysam Taassori, Ph.D. October 2020, Low Overhead Secure Systems, First employment: AMD Research.
• Vivek Venkatesan, M.S. December 2007, Criticality of On-Chip Wires , First employment: Oracle, Current employment: Facebook.
• Byong Wu Chong, M.S. December 2012, Transactional Memory , First employment: Broadcom, Current employment: Amazon.
• Gita Sreekumar, M.S. December 2014, First employment: Qualtrics.
• Sahil Koladiya, M.S. May 2015, First employment: Cisco, Current employment: Amazon.
• Akhila Gundu, M.S. May 2015, First employment: Micron.
• Arjun Deb, M.S. May 2016, First employment: Xilinx, Current employment: Apple.
• Chandru Nagarajan, M.S. May 2017, First employment: Micron, Current employment: Apple.
• Shirley Hon, M.S. December 2018.

Current:

• Surya Narayanan, Ph.D. student, Neuromorphic Architectures
• Sumanth Gudaparthi, Ph.D. student, Deep Learning Accelerators
• Ananth Krishna Prasad, Ph.D. student, Acceleration with Resistive Memories
• Sarabjeet Singh, Ph.D. student, Acceleration of Security Primitives
• Lin Jia, Ph.D. student, Machine Learning Systems
• Shreyas Singh, Ph.D. student, Near Data Processing

Life outside work

Plenty of golf. Plenty of caddying for my two kids. Terrible guitar renditions of songs by Tool. Defending my kitchen countertops from a boisterous German Shepherd.