Rajeev Balasubramonian

Professor
School of Computing
University of Utah

CV | Detailed research page | Full publication list | Teaching page | Utah Arch Research Group | Blog | YouTube

Research

Recent Activities:

• HPCA 2019 Program Co-Chair.
• Tutorial on Runtimes in the Cloud , co-located with ISCA 2018.
• IEEE Micro Special Issue on Near Data Processing , guest co-editor, Jan/Feb 2016.
• 3rd Workshop on Near-Data Processing , co-located with MICRO 2015.
• 2nd Workshop on Near-Data Processing , co-located with MICRO 2014.
• The Memory Forum , co-located with ISCA 2014.
• ASPLOS 2014
• 1st Workshop on Near-Data Processing , co-located with MICRO 2013.
• JWAC Memory Scheduling Championship at ISCA 2012, based on the USIMM memory system simulation infrastructure.
• Book: Multi-Core Cache Hierarchies.

Recent Papers (Full list of publications) :

• ASPLOS 2018: VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures.
• HPCA 2018: Secure DIMM: Moving ORAM Primitives Closer to Memory. Lightning talk video
• ACM TACO 2017: CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.
• IJCNN 2017: INXS: Bridging the Throughput and Energy Gap for Spiking Neural Networks.
• ICCD 2016: Enabling Technologies for Memory Compression: Metadata, Mapping, and Prediction.
• ICCD 2016: Understanding and Alleviating Intra-Die and Intra-DIMM Parameter Variation in the Memory System.
• ISCA 2016: ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. Videos: Part I and Part II. Top Picks Honorable Mention
• IEEE Solid-State Circuits Magazine: Making the Case for Feature-Rich Memory Systems: The March Toward Specialized Systems.
• ISPASS 2016: Addressing Service Interruptions in Memory with Thread-to-Rank Assignment. Best Paper Award
• MICRO 2015: Efficiently Prefetching Complex Address Patterns.
• MICRO 2015: Avoiding Information Leakage in the Memory Controller with Fixed Service Policies.
• ICCD 2015: Improving Memristor Memory with Sneak Current Sharing.
• ICCD 2015: Fixed-Function Hardware Sorting Accelerators for Near Data MapReduce Execution.
• HPCA 2015: Overcoming the Challenges of Crossbar Resistive Memory Architectures.
• SC 2014: Managing DRAM Latency Divergence in Irregular GPGPU Applications.
• IEEE Micro Special Issue on Big Data 2014: Comparing Implementations of Near Data Computing with In-Memory MapReduce Workloads.
• IEEE Micro Special Issue on Big Data 2014: Near-Data Processing: Insight from a Workshop at MICRO-46.
• ISPASS 2014: NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce Workloads.
• HPCA 2014: MemZip: Exploiting Unconventional Benefits from Memory Compression.
• HPCA 2014: Sandbox Prefetching: Safe, Run-Time Evaluation of Aggressive Prefetchers. Top Picks Honorable Mention

Other Selected Publications (Full list of publications) :

• MICRO 2013: Quantifying the Relationship between the Power Delivery Network and Architectural Policies in a 3D-Stacked Memory Device.
• HPCA 2013: A Novel System Architecture for Web Scale Applications Using Lightweight CPUs and Virtualized I/O.
• MICRO 2012: Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.
• ISCA 2012: LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems.
• HPCA 2012: Efficient Scrub Mechanisms for Error-Prone Emerging Memories.
• HPCA 2012: Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads.
• ISCA 2011: Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems.
• TOP PICKS 2011: CHOP: Integrating DRAM Caches for CMP Server Platforms.
• PACT 2010 Best Paper: Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers.
• ISCA 2010: Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores.
• ASPLOS 2010: Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement.
• HPCA 2010: Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks.
• HPCA 2010: CHOP: Adaptive Filter-based DRAM Caching for CMP Server Platforms.
• HPCA 2009: Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches.
• HPCA 2009: Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy.
• TOP PICKS 2008: Architecting Efficient Interconnects for Large Caches with CACTI 6.0.
• MICRO 2007: Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0.
• MICRO 2007: Leveraging 3D Technology for Improved Reliability.
• ISCA 2007: Interconnect Design Considerations for Large NUCA Caches.
• ISCA 2006: Interconnect-Aware Coherence Protocols for Chip Multiprocessors.
• HPCA 2005: Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.

• Neuromorphic Architectures : designing accelerators and biology-inspired architectures for cognitive or machine-learning applications.
• Memory Systems : optimizing DRAM/NVM chips, memory controllers, data placement, and security for big-data and datacenter workloads.

• Reliability : efficient mechanisms to support chipkill reliability in the memory system.
• Large cache design : methodologies to model large NUCA cache hierarchies, policies to organize data, and organizations in 3D.
• Interconnect design : leveraging different wires in a heterogeneous network for architectural innovation.
• Transactional memory : innovations for scalable hardware transactional memory.

Book

Multi-Core Cache Hierarchies , Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar, Synthesis Lectures in Computer Architecture , Morgan and Claypool Publishers, 2011.

Software Release

CACTI 7

USIMM

CACTI 6.0 ( CACTI mirror site )

Teaching

In Fall 2017, I am teaching a special topics class on Neuromorphic Architectures (CS 7960). I typically teach CS 7810 Advanced Computer Architecture, CS 6810 Computer Architecture, CS 3810 Computer Organization, and the Architecture/VLSI Seminar (CS 7937). Courses taught in the past are listed here.

Students

Graduated:

• Naveen Muralimanohar , Ph.D. September 2008, Wire-Aware Cache Architectures , First employment: HP Labs, Current employment: Amazon.
• Niti Madan , Ph.D. January 2009, Leveraging Mixed-process 3D Die Stacking Technology for Cache Hierarchies and Reliability , First employment: Computing Innovation Fellow at IBM T.J. Watson, Current employment: AMD Research.
• Manu Awasthi , Ph.D. September 2011, Managing Data Locality in Future Memory Hierarchies Using a Hardware Software Co-Design Approach , First employment: Micron, Current employment: IIT Gandhinagar.
• Aniruddha Udipi , Ph.D. March 2012, Designing Efficient Memory for Future Computing Systems , First employment: ARM, Current employment: Google.
• Kshitij Sudan , Ph.D. October 2012, Data Placement for Efficient Main Memory Access , First employment: Samsung, Current employment: ARM.
• Niladrish Chatterjee , Ph.D. September 2013, Designing Efficient Memory Schedulers for Future Systems , First employment: NVidia.
• Seth Pugsley , Ph.D. May 2014, Opportunities for Near Data Computing in MapReduce Workloads , First employment: Intel.
• Manju Shevgoor , Ph.D. October 2015, Enabling Big Memory with Emerging Technologies, First employment: Intel.
• Ali Shafiee , Ph.D. August 2017, Hardware Accelerators for Deep Learning, First employment: Samsung.
• Vivek Venkatesan , M.S. December 2007, Criticality of On-Chip Wires , First employment: Sun (currently, Oracle).
• Byong Wu Chong, M.S. December 2012, Transactional Memory , First employment: Broadcom.
• Gita Sreekumar, M.S. December 2014, First employment: Qualtrics.
• Sahil Koladiya, M.S. May 2015, First employment: Cisco, Current employment: Amazon.
• Akhila Gundu, M.S. May 2015, First employment: Micron.
• Arjun Deb, M.S. May 2016, First employment: Xilinx.
• Chandru Nagarajan, M.S. May 2017, First employment: Micron.

Current:

• Meysam Taassori, Ph.D. student, DRAM Variation
• Karl Taht, Ph.D. student, Prefetching
• Anirban Nag, Ph.D. student, Machine Learning Accelerators
• Surya Narayanan, Ph.D. student, Neuromorphic Architectures
• Shirley Hon, M.S. student, Memory Compression

Life outside work

My blood pressure as an Assistant Professor was 30 points lower than what it was as a grad student. Must have something to do with a wonderful wife and a wonderful sport.