HomePage
I am a 5th year PhD candidate working in the Utah Arch group under the guidance of Dr. Rajeev Balasubramonian.
My research in Computer Architecture involves energy and performance optimization of memory hierarchies - especially the main memory. I am exploring DRAM and NVM microarchitectures coupled with memory controller optimizations for performance and energy efficiency. I am also interested in the implications of application and runtime characteristics on memory design for current and future systems.
In the past, I have interned at the Intelligent Infrastructure Lab at HP (Fall 2012) and at AMD Research (Spring 2012).
I obtained my bachelor's in engineering (BE) degree from Jadavpur University, India and worked for a year designing CAD tools at the EDA vendor Atrenta. I joined the U in Fall 2008.
USIMM: USIMM is a cycle accurate DRAM simulator that I co-developed with folks at the Utah Arch lab. It was used as athe simulation infrastructure for the JWAC Memory Scheduling Championship at ISCA 2012. USIMM can be downloaded from this link.
