Nil Chatterjee

Niladrish Chatterjee

Sr. Research Scientist @ NVIDIA

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I am a computer architect in NVIDIA Research. My research focuses on realizing energy-efficient, high-performance memory and processor architectures that will power future supercomputers and artificially intelligent machines. I received my PhD in computer engineering from the University of Utah under the guidance of Dr. Rajeev Balasubramonian in 2013. I interned at AMD Research and HP Labs in the spring and fall of 2012, respectively, and developed EDA tools for Atrenta (now Synopsis) for a year in India after receiving my B.E. degree from Jadavpur University (2007).


9,361,955 Memory Access Methods and Apparatus (issued 06/07/16)
9,489,321 Scheduling memory accesses using an efficient row burst value (issued 11/08/16)
9,535,831 Page migration in a 3D stacked hybrid memory (issued 01/03/17)


Most publications are copyrighted by the IEEE or the ACM. Please respect these copyrights. Typically, personal or classroom use is granted; papers cannot be duplicated for commercial purposes.

SC'17 Towards Standardized Near-Data Processing with Unrestricted Data Placement for GPUs
Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Kevin Hsieh
30th IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), Denver, USA, 2017.

ARXIV Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Stephen W. Keckler.
arxiv, 2017.

SIGMETRICS'17 Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Keving K. Chang, Abdulla Giray Yaglikci, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hassan Hassan, Onur Mutlu.
Proceedings of the ACM on Measurement and Analysis of Computer Systems (SIGMETRICS), Champaign-Urbana, USA, 2017.

HPCA-23 Architecting an Energy-Efficient DRAM System For GPUs
Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally.
23rd International Symposium on Higher Performance Computer Architecture (HPCA), Austin, USA, 2017.
Coverage on The Next Platform

ISCA-43 Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Stephen W. Keckler.
43rd ACM/IEEE International Symposium on Computer Architecture (ISCA), Seoul, S. Korea, 2016.

ISPASS'16 Addressing Service Interruptions in Memory with Thread-to-Rank Assignment
Manjunath Shevgoor, Rajeev Balasubramonian, Niladrish Chatterjee, Jung-Sik Kim.
17th IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Uppsala, Sweden, 2016.
Best Paper Award

MEMSYS'16 CLARA: Circular Linked-List Refresh Architecture
Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel Emer, Stephen W. Keckler
International Symposium on Memory Systems (MEMSYS). Washington D.C., USA, 2016.

MEMSYS'15 Anatomy of GPU Memory System for Multi-Application Execution
Adwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Stephen W. Keckler, Mahmut T. Kandemir, Chita R. Das
International Symposium on Memory Systems (MEMSYS). Washington D.C., USA, 2015.

SC'14 Managing DRAM Latency Divergence in Irregular GPGPU Applications
Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian
27th IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), New Orleans, USA, 2014.

MICRO-46 Quantifying the Relationship between the Power-Delivery Network and Architectural Policies in 3-D Stacked Memory Devices
Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha Udipi
46th ACM/IEEE International Symposium on Microarchitecture (MICRO). Davis, USA, 2013.

MICRO-45 Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access
Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi Iyer
45th ACM/IEEE International Symposium on Microarchitecture (MICRO). Vancouver, Canada, 2012.

HPCA-18 Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads
Niladrish Chatterjee, Rajeev Balasubramonian, Naveen Muralimanohar, Al Davis, Norm Jouppi
18th International Symposium on High Performance Computer Architecture (HPCA). New Orleans, USA, 2012.

ASPLOS-15 Micro-pages: Increasing DRAM Efficiency with Locality-Aware Data Placement
Kshitij Sudan, Niladrish Chatterjee, Dave Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis
15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Pittsburgh, USA, 2010.

ISCA-37 Rethinking DRAM Design and Organization for Energy-Constrained Multi-cores
Aniruddha Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norm Jouppi
37th ACM/IEEE International Symposium on Computer Architecture (ISCA). St. Malo, France, 2010.

Tutorials, Workshops, and Technical Reports

SIGGRAPH'14 Why Graphics Programmers Need to Know About DRAM
Erik Brunvand, Daniel Kopta, Niladrish Chatterjee
Course at the 41st International Conference and Exhibition on Computer Graphics and Interactive Techniques, Vancouver, Canada, 2014.

WACAS'14 Exploring a Brink-of-Failure Memory Controller to Design an Approximate Memory System
Meysam Taassori, Niladrish Chatterjee, Ali Shafiee, Rajeev Balasubramonian
1st Workshop on Approximate Computing Across the System Stack (WACAS),held in conjunction with ASPLOS-2014, Salt Lake City, USA, 2014.

WEED'13 Understanding the Role of the Power Delivery Network in 3D-Stacked Memory Devices
Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian
5th Workshop on Energy-Efficient Design (WEED), held in conjunction with ISCA-2013, Tel Aviv, Israel 2013.

UUCS-12-002 USIMM: the Utah Simulated Memory Module. A Simulation Infrastructure for the JWAC Memory Scheduling Competition
Niladrish Chatterjee, Rajeev Balasubramonian, Manjunath Shevgoor, Seth H. Pugsley, Aniruddha N. Udipi, Ali Shaifei, Manu Awasthi, Kshitij Sudan, Zeshan Chishti
University of Utah Technical Report, 2012.

UCAS-5 Optimizing a Multi-Core Processor for Message Passing Workloads
Niladrish Chatterjee, Seth Pugsley, Josef Spjut, Rajeev Balasubramonian
5th Workshop on Unique Chips and Systems, held in conjunction with ISPASS-2009, Boston, USA, 2009.


Conference Program Committee Member: IPDPS 2017, ICS 2016
Conference Review Committee Member: ISCA 2015, HPCA 2015
External Reviewer: ISCA 2014, MICRO 2012, HPCA 2012, IISWC 2010.