NITI MADAN

I have graduated and I am now a NSF/CRA Computing Innovation Fellow at IBM T.J. Watson mentored by Pradip Bose and Murali Annavaram at USC. I received my PhD under the guidance of Prof. Rajeev Balasubramonian at the University of Utah. My research focuses on power and reliability-aware architectures and leveraging emerging technologies such as 3D die stacking. I am also interested in memory hierarchy design and analytical models for many-core systems. Please see my CV for more details.

PUBLICATIONS

• Guarded Power Gating in a Multi-core Setting, Niti Madan, Alper Buyuktosunoglu, Pradip Bose and Murali Annavaram, 17th International Symposium on High-Performance Computer Architecture (HPCA-17), February 2011
• Guarded Power Gating in a Multi-core Setting, Niti Madan, Alper Buyuktosunoglu, Pradip Bose and Murali Annavaram, 2nd Workshop on Energy Efficient Design (WEED) held in conjunction with ISCA, June 2010
• Power-efficient, Reliable Microprocessor Architectures: Modeling and Design Methods, Several researchers at T.J. Watson Research Center, ACM Great Lakes Symposium on VLSI (GLVLSI), May 2010
• CHOP: Adaptive Filter-based DRAM Caching for CMP Server Platforms , Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravi Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , January 2010
• Optimizing Capacity and Communication in a 3D Stacked Reconfigurable Hierarchy, Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishanker Iyer, Srihari Makineni, and Don Newell, appeared in 15th International Symposium on High-Performance Computer Architecture (HPCA-15), February 2009
• Scalable and Reliable Communication for Hardware Transactional Memory, Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, and Rajeev Balasubramonian, appeared in the 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2008
• Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory, Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, and Rajeev Balasubramonian, Technical Report UUCS-08-001, January 2008 pdf
• Leveraging 3D Technology for Improved Reliability, Niti Madan, Rajeev Balasubramonian, appeared in the 40th International Symposium on Microarchitecture (MICRO-40), December 2007 (pdf)
• Power-efficient Approaches to Redundant Multithreading, Niti Madan, Rajeev Balasubramonian, appeared in IEEE Transactions on Parallel and Distributed Systems (TPDS) Special Issue on CMPs, August 2007 (pdf)
• Exploiting Eager Register Release in a Redundantly Multi-threaded Processor, Niti Madan, Rajeev Balasubramonian, appeared in 2nd Workshop on Architectural Reliability (WAR-2), held in conjunction with MICRO-39, December 2006 (pdf)
• A First-Order Analysis of Power Overheads of Redundant Multi-Threading, Niti Madan, Rajeev Balasubramonian, appeared in 2nd Workshop on System Effects of Logic Soft Errors (SELSE-II), April 2006 (pdf)
• Power-efficient Approaches to Reliability, Niti Madan, Rajeev Balasubramonian, Technical Report UUCS-05-010, December 2005 (pdf)
• Asynchronous Microengines for Network Processing, Niti Madan, Masters Thesis, University of Utah
• A case for Asynchronous Microengines for Network Processing, Niti Madan and Erik Brunvand, appeared in Advanced Networking and Communications Hardware Workshop (ANCHOR 2004) held in conjunction with 31st Annual Symposium in Computer Architecture (ISCA 2004) (pdf)