Naveen Muralimanohar
Graduate Student
Email: naveen at cs.utah.edu
Office: Impulse Lab, MEB (2162)
Tel: (801) 856 4784
I am currently pursuing my Ph.D. in School of Computing at University of Utah. I work with Dr.Rajeev Balasubramonian and my research interests broadly include interconnect design, on-chip caches, coherence protocols, clustered architecture, and processor reliability.
Updates
CACTI 6.0 is now available for download. Please follow this link to get the latest version.
The paper submission site for this year's CMP-MSI workshop (to be held in conjunction with ISCA'08) is up and running. The deadline for the workshop is April 18th.
The workshop accepts two different kinds of papers: regular eight page technical papers or three page position papers on research directions. Check out the main workshop page for more information.
We recently had a colloquium on multi-core architecture. Various research groups at School of Computing expressed their views on chip multi-processor and its influence on their research. More details about the colloqium and the presentation slides can be found here.
I am organizing architecture reading club this semester. Check out the website for the list of papers we will be discussing.