Publication List

Most publications are copyrighted by IEEE or ACM. Please respect these copyrights. Typically, personal or classroom use is granted; papers cannot be duplicated for commercial purposes. In recent years, the research group has been funded by NSF grant CCF-0430063, NSF CAREER award CCF-0545959, and the University of Utah. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation or any other sponsor. Some of our simulation results are derived with Simics that is supported by Virtutech .

Publications

Refereed Conference and Journal Papers

Scalable and Reliable Communication for Hardware Transactional Memory, Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT-17) , Toronto, October 2008.
Architecting Efficient Interconnects for Large Caches with CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi, selected to appear in IEEE Micro's Special issue on Top Picks from 2007 Computer Architecture Conferences , Jan/Feb 2008.
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
Leveraging 3D Technology for Improved Reliability , Niti Madan, Rajeev Balasubramonian, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
Power Efficient Approaches to Redundant Multithreading , Niti Madan, Rajeev Balasubramonian, IEEE Transactions on Parallel and Distributed Systems (Special Issue on CMP Architectures) , Vol. 18, No. 8, pp. 1066-1079, August 2007.
Understanding the Impact of 3D Stacked Layouts on ILP , Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian, The Journal of Instruction-Level Parallelism (JILP) , Volume 9, June 2007.
Interconnect Design Considerations for Large NUCA Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 34th International Symposium on Computer Architecture (ISCA-34) , San Diego, June 2007.
Leveraging Wire Properties at the Microarchitecture Level , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, IEEE Micro , Vol. 26, No. 6, November/December 2006.
Exploring the Design Space for 3D Clustered Architectures , Manu Awasthi, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
The Effect of Interconnect Design on the Performance of Large L2 Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
Interconnect-Aware Coherence Protocols for Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 33rd International Symposium on Computer Architecture (ISCA-33) , Boston, June 2006.
Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity , Naveen Muralimanohar, Karthik Ramani, and Rajeev Balasubramonian, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , Austin, March 2006.
A Case for Increased Operating System Support in Chip Multi-Processors , David Nellans, Rajeev Balasubramonian, and Erik Brunvand, 2nd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, September 2005.
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, and Venkatanand Venkatachalapathy, 11th International Symposium on High-Performance Computer Architecture (HPCA-11) , San Francisco, February 2005.
Cluster Prefetch: Tolerating On-Chip Wire Delays in Clustered Microarchitectures , Rajeev Balasubramonian, 18th International Conference on Supercomputing (ICS-18) , Saint-Malo, June 2004.
Dynamically Tuning Processor Resources with Adaptive Processing , D.H. Albonesi, Rajeev Balasubramonian, S.G. Dropsho, S. Dwarkadas, E.G. Friedman, M.C. Huang, V. Kursun, G. Magklis, M.L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P.W. Cook, and S.E. Schuster, IEEE Computer, Special Issue on Power-Aware Computing , Vol.36, No.12, December 2003.
A Dynamically Tunable Memory Hierarchy , Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, IEEE Transactions on Computers , Vol.52, No.10, pp.1243-1258, October 2003.
Dynamically Managing the Communication-Parallelism Trade-Off in Future Clustered Processors , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 30th International Symposium on Computer Architecture (ISCA-30) , San Diego, June 2003.
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power , Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigoris Magklis, and Michael Scott, 11th International Conference on Parallel Architectures and Compilation Techniques (PACT) , pp. 141-152, Charlottesville, September 2002.
Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling , Greg Semeraro, Grigoris Magklis, Rajeev Balasubramonian, David Albonesi, Sandhya Dwarkadas, and Michael Scott, 8th International Symposium on High-Performance Computer Architecture (HPCA-8), pp. 29-40, Cambridge, February 2002.
Reducing the Complexity of the Register File in Dynamic Superscalar Processors , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 34th International Symposium on Microarchitecture (MICRO-34), pp. 237-248, Austin, December 2001.
Dynamically Allocating Processor Resources Between Nearby and Distant ILP , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 28th International Symposium on Computer Architecture (ISCA-28) , pp. 26-37, Göteborg, July 2001.
Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, 33rd International Symposium on Microarchitecture (MICRO-33) , pp. 245-257, Monterey, December 2000.

Refereed Workshop Papers

Exploiting Eager Register Release in a Redundantly Multi-Threaded Processor , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on Architectural Reliability (WAR-2), held in conjunction with MICRO-39, Orlando, December 2006.
Leveraging Bloom Filters for Smart Search Within NUCA Caches , Robert Ricci, Steve Barrus, Dan Gebhardt, Rajeev Balasubramonian, 7th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-33 , Boston, June 2006.
Re-Visiting the Performance Impact of Microarchitectural Floorplanning , Anupam Chakravorty, Abhishek Ranjan, Rajeev Balasubramonian, 3rd Workshop on Temperature Aware Computer Systems (TACS), held in conjunction with ISCA-33 , Boston, June 2006.
A First-Order Analysis of Power Overheads of Redundant Multi-Threading , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on the System Effects of Logic Soft Errors (SELSE-2) , Urbana, April 2006.
Wire Management for Coherence Traffic in Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 6th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-32 , Madison, June 2005.
Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors , Karthik Ramani, Naveen Muralimanohar, and Rajeev Balasubramonian, 5th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-31 , Munich, June 2004.
Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches , Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, and Alper Buyuktosunoglu, 3rd Workshop on Power-Aware Computer Systems (PACS), held in conjunction with MICRO-36 , San Diego, December 2003.
Dynamic Memory Hierarchy Performance Optimization , Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, Workshop on Solving the Memory Wall Problem , held in conjunction with the 27th ISCA, Vancouver, June 2000.

Technical Reports

Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, Technical Report UUCS-08-001, January 2008.
Commit Algorithms for Scalable Hardware Transactional Memory , Seth H. Pugsley, Rajeev Balasubramonian, Technical Report UUCS-07-016, August 2007.
Power-Efficient Approaches to Reliability , Niti Madan, Rajeev Balasubramonian, Technical Report UUCS-05-010, December 2005.
Dynamic Management of Microarchitecture Resources in Future Microprocessors , Rajeev Balasubramonian, Ph.D. Thesis, Department of Computer Science, University of Rochester, August 2003.
Microarchitectural Trade-offs in the Design of a Scalable Clustered Microprocessor , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, URCS Technical Report #771, January 2002.
A High-Performance Two-Level Register File Organization , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, URCS Technical Report #745, Apr 2001.
Dynamically Allocating Processor Resources between Nearby and Distant ILP , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, URCS Technical Report #743, Apr 2001.

Patents

Multiple Clock Domain Microprocessor, David H. Albonesi, Greg Semeraro, Grigoris Magklis, Michael L. Scott, Rajeev Balasubramonian, and Sandhya Dwarkadas, US Patent No. 7,089,443, issued Aug 8 2006.
Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, US Patent No. 6,834,328, issued Dec 21 2004.
Dynamically Reconfigurable Memory Hierarchy, Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, US Patent No. 6,684,298, issued Jan 27 2004.
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures, R. Balasubramonian, N. Muralimanohar, K. Ramani, L. Cheng, J. Carter, Provisional US Patent filed, February 2006.
Dynamically Managing the Communication-Parallelism Trade-off in Clustered Processors, R. Balasubramonian, S. Dwarkadas, D.H. Albonesi, Provisional US Patent filed, June 2004.