CS/ECE 6810: Computer Architecture

Course Information

  • Time: Mon/Wed 11:50AM - 01:10PM
  • Location: CSC 205
  • Instructor: Mahdi Nazm Bojnordi, email: lastname@cs.utah.edu, office hours: email me for appoitment, MEB 3418
  • Teaching Assistants: Payman Behnam, email: paymanbehnam@gmail.com, office hours: Thu 11:00AM - 01:00PM, MEB 3423; Krunal Jain, email: krunal.bitsy@gmail.com, office hours: Tue 09:30AM - 11:30PM, MEB 3423
  • Pre-Requisite: CS 3810 or equivalent
  • Textbook: Computer Architecture A Quantitative Approach - 5th Edition, John Hennessy and David Patterson
  • Canvas is the main venue for class announcements, homework assignments, and discussions.

Important Policies

Please refer to the College of Engineering Guidelines for disabilities, add, drop, appeals, etc. Notice that we have zero tolerance for cheating; as a result, please read the Policy Statement on Academic Misconduct, carefully. Also, you should be aware of the SoC Policies and Guidelines.

Class rosters are provided to the instructor with the student's legal name as well as "Preferred first name" (if previously entered by you in the Student Profile section of your CIS account). While CIS refers to this as merely a preference, I will honor you by referring to you with the name and pronoun that feels best for you in class, on papers, exams, group projects, etc. Please advise me of any name or pronoun changes (and please update CIS) so I can help create a learning environment in which you, your name, and your pronoun will be respected.

Grading

The following items will be considered for evaluating the performance of students.

Fraction Notes
Homework Assignments 30% as scheduled below
Midterm Exam 30% 11:50AM - 01:00PM, Mon., October 15th
Final Exam 40% 10:30AM - 12:30PM, Thu., December 13th

Homework Assignments

Homework assignments will be released on Canvas; all submissions must be made through Canvas. Only those submissions made before midnight will be accepted. Any late submission will be considered as no submission.

Release Date Submission Deadline
Homework 1 Sep. 5th Sep. 12th
Homework 2 Sep. 26th Oct. 3rd
Homework 3 Oct. 31st Nov. 07th
Homework 4 Nov. 28th Dec. 05th

Class Schedule (subject to change)

The following is a tentative class schedule that may be updated on a week-by-week basis during the course semester.

Date Lecture Required Reading Recommended Reading Assignment Release
08/20 Logistics and Introduction Sections 1.1-1.4 Moore, "Cramming more components onto integrated circuits," Electronics Magazine, 1965.
Please watch the Turing Lecture at ISCA 2018.
08/22 Performance Metrics Sections 1.4-1.9
08/27 Instruction Set Architecture Appendix A Charles Price, "MIPS IV Instruction Set," MIPS Technologies, Inc., 1995
08/29 Pipelining: Introduction Appendix C.1
09/05 Pipelining: Hazards Appendix C.2 Homework 1
09/10 Pipelining: Branch and Multicycle Instructions Appendix C.4-C.5
09/12 ILP: Introduction Section 3.1
09/17 ILP: Compiler-based Techniques Section 3.2 Nicolau and Fisher, "Measuring the Parallelism Available for Very Long Instruction Word Architectures," IEEE Transactions on Computers, 1984
09/19 ILP: Control Flow Section 3.3
09/24 Branch Predictors Section 3.3
09/26 Dynamic Scheduling Section 3.4 Sodani and Sohi, "Dynamic Instruction Reuse," International Symposium on Computer Architecture, 1997 Homework 2
10/01 Out-of-Order Execution Section 3.5 Sohi, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers," IEEE Transactions on Computers, 1990
10/03 Midterm Review
10/08 Fall Break
10/10 Fall Break
10/15 Mid-Term Exam
10/17 Hardware-Based Speculation Sections 3.6-3.9
10/22 Load-Store Queue Sections 3.10-3.12
10/24 Memory Hierarchy Design Appendix B
10/29 Cache Architecture Appendix B Wilkes, "Slave Memories and Dynamic Storage Allocation," IEEE Transactions on Electronic Computers, 1965
10/31 Cache Optimization Sections 2.1-2.3 Akanksha Jain and Calvin Lin, "Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement," International Symposium on Computer Architecture, 2016 Homework 3
11/05 Virtual Memory Section 2.4
11/07 Address Translation and TLB Section 2.5
11/12 Main Memory System Section 2.5
11/14 DRAM Controller Sections 4.1-4.3
11/19 Advanced Memory Controllers Sections 4.1-4.3 Mahdi Nazm Bojnordi and Engin Ipek. "PARDIS: A Programmable Memory Controller for the DDRx Interfacing Standards," International Symposium on Computer Architecture, 2012
11/21 Data-Level Parallelism Sections 4.1-4.3
11/26 Graphics Processing Units Section 4.4
11/28 Thread-Level Parallelism Sections 5.1-5.2 Tullsen et al., "Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor," International Symposium on Computer Architecture, 1996 Homework 4
12/03 Parallel Memory Architecture Sections 5.3-5.4
12/05 Shared Memory Systems Section 5.6 Sarita Adve and Kourosh Gharachorloo "Shared memory consistency models: A tutorial," Computer 29.12, pp. 66-76, 1995