//-size (bytes) 4096 //-size (bytes) 1048576 //-size (bytes) 2097152 -size (bytes) 8388608 //-size (bytes) 16777216 //-size (bytes) 33554432 //-size (bytes) 134217728 //-size (bytes) 67108864 //-size (bytes) 1073741824 //-block size (bytes) 8 -block size (bytes) 128 // To model Fully Associative cache, set associativity to zero //-associativity 2 -associativity 16 -read-write port 1 -exclusive read port 0 -exclusive write port 0 -single ended read ports 0 // Multiple banks connected using a h-tree bus -UCA bank count 1 //-technology (u) 0.032 //-technology (u) 0.045 -technology (u) 0.068 //-technology (u) 0.090 // Bus width include data and address //-output/input bus width 16 -output/input bus width 256 // 300-400 in steps of 10 -operating temperature (K) 350 // to model special structure like branch target buffers, directory, etc. // change the tag size parameter // if you want cacti to calculate the tagbits, set the tag size to "default" -tag size (b) "default" //-tag size (b) 45 // fast - data and tag access happen in parallel // sequential - data array is accessed after accessing the tag array // normal - data array lookup and tag access happen in parallel // final data block is broadcasted in data array h-tree // after getting the signal from the tag array -access mode (normal, sequential, fast) - "sequential" //NOTE: CACTI 5.0 assumes SRAM tags for a DRAM cache //-cache type (SRAM - only data array , SRAM_CACHE - tag & data array, DRAM_CACHE) - "SRAM" -cache type (SRAM - only data array , SRAM_CACHE - tag & data array, DRAM_CACHE) - "SRAM_CACHE" //-cache type (SRAM - only data array , SRAM_CACHE - tag & data array, DRAM_CACHE) - "DRAM_CACHE" // DESIGN OBJECTIVE for UCA (or banks in NUCA) -design objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:0 // Percentage deviation from the minimum value // Ex: A deviation value of 10:1000:1000:1000:1000 will try to find an organization // that compromises at most 10% delay. // NOTE: Try reasonable values for % deviation. Inconsistent deviation // percentage values will not produce any valid organizations. For example, // 0:0:100:100:100 will try to identify an organization that has both // least delay and dynamic power. Since such an organization is not possible, CACTI will // throw an error. Refer CACTI-6 Technical report for more details -deviate (delay, dynamic power, leakage power, cycle time, area) 20:100000:100000:100000:1000000 // Objective for NUCA -NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:0 -NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:1000:10000:10000:10000 // Set optimize tag to ED or ED^2 to obtain a cache configuration optimized for // energy-delay or energy-delay sq. product // Note: Optimize tag will disable weight or deviate values mentioned above -Optimize ED or ED^2 (ED, ED^2, NONE): "ED" //-Optimize ED or ED^2 (ED, ED^2, NONE): "ED^2" //-Optimize ED or ED^2 (ED, ED^2, NONE): "NONE" -Cache model (NUCA, UCA) - "NUCA" // In order for the CACTI to find the optimal NUCA bank value the following // variable should be assigned 0. -NUCA bank count 0 // NOTE: for nuca network frequency is set to a default value of // 5GHz in time.c. CACTI automatically // calculates the maximum possible frequency and downgrades this value if necessary // By default CACTI considers both full-swing and low-swing // wires to find an optimal configuration. However, it is possible to // restrict the search space by changing the signalling from "default" to // "fullswing" or "lowswing" type. -wire signalling (fullswing, lowswing, default) - "default" //-wire signalling (fullswing, lowswing, default) - "lowswing" // Contention in network (which is a function of core count and cache level) is one of // the critical factor used for deciding the optimal bank count value -Core count 16 -Cache level (L2/L3) - "L2" -Print level (DETAILED, CONCISE) - "DETAILED" //-Print level (DETAILED, CONCISE) - "CONCISE"