Digital VLSI Chip Design
with Cadence and Synopsys
CAD Tools

UofU_Digital_v1_2

Please note that all this information is provided "as is" and without any warranty of any kind. Please use the information at your own risk. This warning is especially true of the cell libraries!

NEW (May 2011) - the UofU_Digital_v1_2 cell library is now available in both CDB (Cadence IC v5) and OA (Cadence IV v6) versions.

This is a basic CMOS cell library that can be used with the examples in the book. It is built using the CMOS cell template described in Chapter 6 of the book and is designed to be used with the ON (formerly AMI) C5N 0.5 micron CMOS process through the MOSIS SCN3M_SUBM process description. It uses both metal1 and metal2 inside the cells, but not metal3. The metal1 is used both in horizontal and vertical routing, but metal2 is used only as vertical and, as much as possible, is restricted to be on the metal2 routng grid as defined in Chapter 6. Connection points are all on metal2.

This library includes cmos_sch, schematic, behavioral (Verilog), layout, extracted, analog_extracted, and abstract views. The behavioral views include "specify" blocks so that simulation may be done with back-annotated sdf timing. These cells use the UofU_TechLib_ami06 technology library, and the transistors in the cmos_sch views use transistors from the UofU_Analog_Parts library. This means that when simulated using a Verilog simulator at a transistr switch level, the transistors all have 0.1 units of delay. If you have not installed the UofU_Analog_parts library, or prefer the transistors to be simulated using a zero-delay model, you can use the Edit->RenameReferenceLibrary command in the Library Manager to change all library references of UofU_Analog_Parts to be NCSU_Analog_Parts instead (using the NCSU CDK). The transistors in NCSU_Analog_Parts have zero delay simulation models.

This library includes UofU_Digital_v1_2.lib, .db, .lef, and.v files for use with the CAD tools as described in the book.

Access to this library is protected by password. This is so instructors can choose to limit access to this library as students are developing their own library. Instructors, or other non-student users, please contact Erik Brunvand (elb at cs.utah.edu) for username and password information.Tell me who you are and what you're planning on doing with the library.

The gzipped tar files for both the CDB and OA versions of UofU_Digital_v1_2 are here (password protected)

To use the library, simply untar the UofU_Digital_v1_2 directory from the gzipped tar file. Then point to the location where you put the UofU_Example library directory in your cds.lib file. You can put this in the NCSU CDK cds.lib file in $CDK_DIR/cdssetup/cds.lib, or in the $LOCAL_CADSETUP/cadence/cds.lib file, or in the cds.lib file that is in the directory from which you start the Cadence tools. The format in the cds.lib file is:

DEFINE UofU_Digital_v1_2 <path-to-the-directory>/UofU_Digital_v1_2

The cells in this library have their names coded with output drive strength. All strengths are relative to a unit (X1) inverter's drive. A unit-drive inverter in this library uses an nmos device with length 0.6 microns (drawn), and width 3.0 microns. The pmos is 0.6 microns long and 6.0 microns wide.

The cells in the library are:

AND3X1: 3-input AND
AOI21X1, AOI22X1: AND-OR-Inv gates
BUFX2, BUFX4, BUFX8: non-inverting buffers
DCBNX1, DCBX1, DCNX1, DCX1: D-type flip flops with active-low clear. B means that the device includes both Q and QB outputs. N means an active-low clock.
ENINVX1, ENINVX2: enabled(tri-state) inverters
FILL, FILL2, FILL4, FILL8: filler cells of different widths for filling in the standard cell rows after placement
INVX1, INVX16, INVX2, INVX4, INVX8: inverters
LCNX1, LCX1: level-sensitive (gated) latches with active-low clear. N means active-low gate
MUX2NX1, MUX2X2: 2-way muxes. N means an inverting mux
NAND2X1, NAND2X2, NAND3X1: NAND gates with 2 and 3 inputs
NOR2X1, NOR2X2, NOR3X1: NOR gates with 2 and 3 inputs
OAI21X1 OAI22X1: OR-AND-Inv gates
TIEHI, TIELO: Cells used to tie inputs high or low
XNOR2X1: 2-input XNOR
XOR2X1: 2-input XOR

UofU_Digital_v1_2.db: compiled library file for use with Synopsys Design Compiler
UofU_Digital_v1_2.lef: layout information file used with place and route tools
UofU_Digital_v1_2.lib: library characterization file
UofU_Digital_v1_2.v: Verilog interface and simulation behavior file

Last modified May 18, 2011.