CS/ECE 7810: Advanced Computer Architecture

Course Information

  • Time: Mon/Wed 11:50-01:10PM
  • Location: CANVAS
  • Instructor: Mahdi Nazm Bojnordi, email: lastname@cs.utah.edu, office hours: email me for appointment, MEB 3418
  • Pre-Requisite: CS/ECE 6810
  • Textbook: "Memory Systems: Cache, DRAM, Disk", Jacob et al.
  • Textbook: "Principles and Practices of Interconnection Networks", Dally and Towles.
  • Textbook: "Parallel Computer Architecture", Culler, Singh, Gupta.
  • "Synthesis Lectures on Computer Architecture", Morgan & Claypool Publishers.
  • Canvas is the main venue for class announcements, homework assignements, and discussions.
  • Description: This course is based on advanced topics in computer architecture, including cache energy innovations, memory system optimizations, interconnection networks, cache coherence protocols, and emerging computation models.
  • Expectation: In addition to homework assignment and final exam, students are expected to present a conference paper related to their course project in April. A project presentation is expected for each group of students in the last two classes and a final project reports is due in May. Important dates are listed below.

Important Policies

Please refer to the College of Engineering Guidelines for disabilities, add, drop, appeals, etc. Notice that we have zero tolerance for cheating; as a result, please read the Policy Statement on Academic Misconduct, carefully. Also, you should be aware of the SoC Policies and Guidelines.

Class rosters are provided to the instructor with the student's legal name as well as "Preferred first name" (if previously entered by you in the Student Profile section of your CIS account). While CIS refers to this as merely a preference, I will honor you by referring to you with the name and pronoun that feels best for you in class, on papers, exams, group projects, etc. Please advise me of any name or pronoun changes (and please update CIS) so I can help create a learning environment in which you, your name, and your pronoun will be respected.

Special Needs

The University of Utah seeks to provide equal access to its programs, services and activities for people with disabilities. If you will need accommodations in the class, reasonable prior notice needs to be given to the Center for Disability Services, 162 Olpin Union Building, 581-5020 (V/TDD). CDS will work with you and the instructor to make arrangements for accommodations. All written information in this course can be made available in alternative format with prior notification to the Center for Disability Services.

Grading

The following items will be considered for evaluating the performance of students.

Fraction Notes
Course Project 50% Creative, simulation based projects done by groups of 2/3 students.
Homework Assignments 20% A homework assignment will be posted in Canvas.
Paper Presentation 10% Every student presents a recent publication related to their course project.
Final Exam 20%

Important Dates

All of the submissions must be made through Canvas.

Date Description
02/03 Project group composition.
02/12 Project proposal.
03/08 The homework assignment will be posted.
03/15 The deadline for the homework assignements (11:59PM).
04/07 Sign up for your student paper presentation.
04/14 Student paper presentations start.
04/21 Student project presentations.
04/26 Take-home final exam.
05/10 Final project report due date.

Class Schedule (subject to change)

The following is a tentative class schedule that may be updated a few hours after each lecture.

Date Lecture Required Reading
01/20 Logistics and Introduction Wilton et al, "An Enhanced Access and Cycle Time Model for On-Chip Caches," Research Report 93/5, 1994
01/25 Cache Power Consumption Powell et al, "Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping," MICRO, 2001
Albonesi, "Selective Cache Ways: On-Demand Cache Resource Allocation," MICRO, 1999
Powell et al, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories," ISLPED, 2000
Kaxiras et al, "Cache decay: exploiting generational behavior to reduce cache leakage power," ISCA, 2001
Flaunter et al, "Drowsy Caches: Simple Techniques for Reducing Leakage Power," ISCA, 2002
01/27 Large Cache Design Qureshi et al, "Adaptive insertion policies for high performance caching," ISCA, 2007
Jaleel et al, "High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)," ISCA, 2010
Qureshi et al, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches," MICRO, 2006
Sanchez et al, "The ZCache: Decoupling Ways and Associativity," MICRO, 2010
02/01 Cache Interconnects Villa et al, "Dynamic Zero Compression for Cache Energy Reduction," MICRO, 2000
Balasubramonian et al, "Microarchitectural Wire Management for Performance and Power in Partitioned Architectures," HPCA, 2005
Kim et al, "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," ASPLOS, 2002
Bojnordi et al, "DESC: Energy-Efficient Data Exchange using Synchronized Counters," MICRO, 2013
02/03 Cache Interconnects 2 Villa et al, "Dynamic Zero Compression for Cache Energy Reduction," MICRO, 2000
Balasubramonian et al, "Microarchitectural Wire Management for Performance and Power in Partitioned Architectures," HPCA, 2005
Kim et al, "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," ASPLOS, 2002
Bojnordi et al, "DESC: Energy-Efficient Data Exchange using Synchronized Counters," MICRO, 2013
02/08 Interconnection Networks Wang et al, "Power-Driven Design of Router Microarchitectures in On-Chip Networks," MICRO, 2003
Gottlieb et al "The NYU Ultracomputer-designing a MIMD, shared-memory parallel machine," ISCA, 1982
Glass et al, "The Turn Model for Adaptive Routing," ISCA, 1992
02/10 Interconnection Networks 2 Wang et al, "Power-Driven Design of Router Microarchitectures in On-Chip Networks," MICRO, 2003
Gottlieb et al "The NYU Ultracomputer-designing a MIMD, shared-memory parallel machine," ISCA, 1982
Glass et al, "The Turn Model for Adaptive Routing," ISCA, 1992
02/17 On-chip Networks Moscibroda et al, "A Case for Bufferless Routing in On-Chip Networks," ISCA, 2009
Feero et al, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," Trans. Computers, 2009
Eghbal et al, "TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip," DFT, 2014
Park et al, "MIRA: A multi-layered on-chip interconnect router architecture," ISCA, 2008
02/22 On-chip Networks 2 Moscibroda et al, "A Case for Bufferless Routing in On-Chip Networks," ISCA, 2009
Feero et al, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," Trans. Computers, 2009
Eghbal et al, "TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip," DFT, 2014
Park et al, "MIRA: A multi-layered on-chip interconnect router architecture," ISCA, 2008
02/24 Snooping Protocols Censier et al, "A new solution to coherence problems in multicache systems," Trans. Computers, 1978
Goodman, "Using cache memory to reduce processor-memory traffic," ISCA, 1983
Papamarcos et al, "A low-overhead coherence solution for multiprocessors with private cache memories," ISCA, 1984
Laudon et al, "The SGI Origin: a ccNUMA highly scalable server," ISCA, 1997
03/01 Memory Synchronization Scott, "Shared-Memory Synchronization," Morgan & Claypool Publishers, 2013
Herlihy et al, "Transactional Memory: Architectural Support for Lock-Free Data Structures," ISCA, 1993
Adve et al, "Shared Memory Consistency Models: A Tutorial," WRL, 1995
03/03 Memory Systems Jacob et al, "Memory Systems: Cache, DRAM, Disk," Morgan Kaufmann, 2007
03/08 DRAM Scheduling Rixner et al, "Memory Access Scheduling," ISCA, 2000
Mutlu et al, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems," ISCA, 2008
Kim et al, "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior," MICRO, 2010
Ipek et al, "Self-Optimizing Memory Controllers: A Reinforcement Learning Approach," ISCA, 2008
03/10 DRAM Addressing and Refresh Zhang et al, "A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality," MICRO, 2000
Ghosh et al "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs," MICRO, 2007
Stuecheli et al, "Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory," MICRO, 2010
03/15 NO CLASS
03/17 DRAM Power Management Liu et al, "Flikker: Saving DRAM Refresh-power through Critical Data Partitioning," ASPLOS, 2011
Liu et al, "RAIDR: Retention-Aware Intelligent DRAM Refresh," ISCA, 2012
Hur et al, "A comprehensive approach to DRAM power management," HPCA, 2008
Seol et al, "Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity," ISCA, 2016
03/22 Memory Reliability Kim et al, "Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors," ISCA, 2014
03/24 Emerging Memory Systems Lee et al, "Architecting Phase Change Memory as a Scalable DRAM Alternative," ISCA, 2009
03/29 Resistive Memory Technology Cho et al, "Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance," MICRO, 2009
Qureshi et al, "Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling," MICRO, 2009
03/31 Reliability of Resisitve Memories Ipek et al, "Dynamically replicated memory: building reliable systems from nanoscale resistive memories," ASPLOS, 2010
Schechter et al, "Use ECP, not ECC, for Hard Failures in Resistive Memories," ISCA, 2010
Seong et al, "SAFER: Stuck-At-Fault Error Recovery for Memories," MICRO, 2010
Yoon et al, "FREE-p: Protecting non-volatile memory against both hard and soft errors," HPCA, 2011
04/07 Processing in Memory Patterson et al, "A Case for Intelligent RAM: IRAM," IEEE Micro, 1997
Guo et al, "AC-DIMM: associative computing with STT-MRAM," ISCA, 2013
04/12 Near Data Processing Gao et al, "HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing," HPCA, 2016
Bojnordi et al, "Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning," HPCA, 2016
04/14 Student Paper Presentation
04/19 Student Paper Presentation
04/21 Course Project Presentation
04/26 Final Exam