The University of Utah uses Cadence tools for courses, research and development, from Verilog simulation to IC design and verification. These tools are used in courses offered by the School of Computing, the Department of Electrical and Computer Engineering, the Computer Engineering Program, and other departments in the College of Engineering.

If you’re considering using the Cadence tools, also consider this book which describes a detailed tutorial flow using the Cadence tools for custom and standard-cell IC design:

Digital VLSI Chip Design with Cadence and Synopsys CAD Tools by Erik Brunvand

Published through Addison-Wesley, 2010
Amazon | Publisher’s site | Book information

New for Fall 2017 – As we do each fall, we’ll be upgrading to newer versions of the basic Cadence tools. These will all fall under the general “v6” category and should be usable with the previously mentioned book (and the V6 transition guide) We will also be making the transition from Encounter Digital Implementation (EDI) to Innovus for place and route this fall.

We may also be offering the Global Foundries 130nm GFUS 8RF-DM technology in addition to the classic On Semi 500nm (C5N) process for students in the CS/ECE 5710/6710 Digital VLSI class. Stay tuned for more details.

New for Fall 2013, 2015- We’ll be upgrading to newer versions of the basic Cadence tools.

From Fall 2012 – If you’re using Digital VLSI Chip Design with Cadence and Synopsys Tools, note that that book uses the v5 tools from Cadence. The examples and tutorials generally work just fine with v6 tools, but there are some slight differences, mostly in the user interface. A revision of the book is in the works, but until that comes out, a conversion guide for using the book with the v6 tools can be found here (linked to the book’s web site)

From Fall 2011 – we’re migrating all the class Cadence scripts and libraries to IC v6.1.5. This is a release of the Cadence suite that uses OpenAccess as the underlying database rather than the older CDB database.

Please note that if you have old CDB data that you’d like to use, you must convert that data to OpenAccess using the cdb2oa converter. Details can be found here.

Cadence Tools in Computer Science
and Electrical and Computer Engineering Courses:
(Most courses that use Cadence tools are cross-listed in CS and ECE)

CS/ECE 5710/6710 – Digital VLSI Design.
This class uses tools from the following bundles: Custom IC, Digital IC, and Verification.
CS/ECE 6770 – Advanced Digital VLSI Design.
This class uses tools from the following bundles: Custom IC, Digital IC, and Verification

CS/ECE 5720/6720 – Analog Integrated Circuit Design. (This courses uses Canvas and does not have a publically accessable web site)
This class uses tools from the following bundles: Verification

CS/ECE 5961/6961 – Relative Timed Asynchronous Design.
This class uses tools from the following byndles: Verification

ECE 6730 – RF Integrated Circut Design. (This courses uses Canvas and does not have a publically accessable web site)
This class uses tools from the following bundles: Custom IC, Verification.

These classes feature advanced design projects using the Cadence tools, and student chip designs are fabricated through the MOSIS foundry service with support from the MOSIS Educational Program (MEP).

Research use of Cadence Tools

• Asynchronous Circuits: This group is involved in understanding how asynchronous and self-timed circuits and systems can be used to build better digital hardware. The research is evolving along four different lines: (i) Investigating different ways to implement self-timed circuits, (ii) using those circuits to build larger self-timed hardware systems, (iii) exploring methods for describing systems as concurrent programs and translating those programs automatically into collections of self-timed circuits, and (iv) theoretical investigations into the properties of these systems. Cadence tools are used in all low-level circuit aspects of this research, including the development of an asynchronous CMOS cell library for use with Cadence place and route tools.
• Hardware Support for Real Time Ray Tracing: The Utah Hardware Ray Tracing group is designing special purpose hardware to implement ray tracing to generate computer graphic images. Ray tracing is creates much higher quality and more realistic images than commodity z-buffer based graphics chips. Ray tracing is more efficient when the scene object database is extremely large or where the primitive objects are not simple triangles, but is considered too slow to work interactively on commodity computers. Recent advances in design tools, hardware processes, and understanding of the ray tracing algorithm makes the project timely and feasible. The end goal of this research is to develop technology to enable commodity ray trace chips that can replace today’s graphics processing units and enable higher quality and more realistic graphics capabilities for future computers.
• APES – Advanced Perceptive Embedded Systems: Ubiquitous computing is a a compelling vision. However before we can expect to naturally interact with computing services that are invisibly embedded into our environment, natural human interfaces will be required. The most obvious need is for speech and visual feature recognition. The biggest problem is that even the best existing speech and visual feature recognizers are heavy-weight applications in the embedded space. They require higher performance than embedded systems can provide and often even performance microprocessors aren’t sufficient. The other problem is that performance processors consume too much power to be tractable in the embedded space. We started out looking for ways to accelerate existing embedded processors with ASIC accelerators and have now settled on a much more general purpose cluster co-processor approach which has a performance/energy level that is similar to ASIC’s while exhibiting much of the generality of convential processors but at a significant performance and energy improvement.
• Utah RF IC lab: At the Utah Radio Frequency Integrated Circuits (RF IC) Laboratory, we research new circuit designs and techniques for advancing the performance of integrated RF systems implemented in silicon process technology. Our integrated circuits are fabricated externally, and we have a complete set of test and measurement facilities on site.

Disclaimer: Information is provided “as is” without warranty or guarantee of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.

Cadence® is a trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134.

Please direct questions about this page to Erik Brunvand (elb at cs dot utah dot edu). Last modified: 8/7/17.