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| I obtained my PhD with my advisor Prof. Ganesh Gopalakrishnan in 2008 and joined Amazon.com. My PhD dissertation is on verification of hierarchical cache coherence protocols for fururistic processors. Before that, I obtained my B.S. from University of Science and Technology of China in 2000 and M.E. from Chinese Academy of Sciences in 2003. |
| Publications |
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Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan and Ching-Tsun Chou Intl. Journal of Formal Methods in System Design, FMSD 2010
Distributed dynamic partial order reduction based verification of threaded software
Automatic discovery of transition symmetry in multithreaded programs using dynamic analysis
Efficient stateful dynamic partial order reduction
Hierarchical cache coherence protocol verification one level at a time through assume guarantee
Transaction based modeling and verification of hardware protocols
Partial order reduction based verification of threaded software
Reducing verification complexity of a multicore coherence protocol using assume/guarantee |
| Other papers |
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An interface aware guided search method for error trace justication in large
protocols Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan and Ching-Tsun Chou Technical report UUCS-08-005, School of Computing, University of Utah
Transaction based modeling and verification of hardware protocols
BT: a bounded transaction model checking for cache coherence protocols
Predicate abstraction for Murphi using CVC-Lite
Performance optimization for a distributed transaction manager
Survey of transaction processing technologies |
| Personal |
| Yu Yang's homepage |