PUBLICATIONS
Towards Scalable, Energy-Efficient,
Bus-Based On-Chip Networks,
Aniruddha N. Udipi, Naveen Muralimanohar (HP Labs), Rajeev Balasubramonian,
16th International Symposium on
on High-Performance Computer Architecture (HPCA-16), Bangalore, January 2010
[pdf]
Acceptance rate: 18%
Non-Uniform Power Access in Large Caches
with Low-Swing Wires,
Aniruddha N. Udipi, Naveen Muralimanohar (HP Labs), Rajeev Balasubramonian,
16th International Conference
on High Performance Computing (HiPC-16), Kochi, December 2009
(Best Paper Award) [pdf]
Acceptance rate: 19%
Optimizing Communication and Capacity
in a 3D Stacked Reconfigurable Cache Hierarchy,
Niti Madan, Li Zhao (Intel),
Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer (Intel),
Srihari Makineni (Intel), Donald Newell (Intel), 15th International Symposium on High-Performance
Computer Architecture (HPCA-15) , Raleigh, February 2009
[pdf]
[ppt]
Acceptance rate: 19%
RESEARCH
My research interests lie primarily in computer engineering and hardware systems. I am currently working on Computer Architecure under Prof. Rajeev Balasubramonian at the University of Utah's School of Computing. Specifically, I am looking at design considerations for next generation scalable interconnects. I am also interested in DRAM and 3-D chip multiprocessors. Earlier, I worked on an ASIC design for an indigenous network processor. This was a DRDO (Defence Research and Development Organization, India) sponsored project under Prof. V. Kamakoti at the Indian Institute of Technology, Madras, India.
INTERNSHIP
Summer 2008: Nehalem Power Foucs Group, Intel OregonCOURSEWORK
Fall 2009
CS 6460 - Operating SystemsSpring 2009
CS 7960 - Advanced Computer ArchitectureCS 5470 - Compilers
Fall 2008
CS 6110 - Formal Methods in System DesignCS 6745 - Testing and Verification of Digital Circuits
Spring 2008
CS 7820 - Advanced Parallel ArchitectureCS 6740 - CAD of Digital Circuits
Fall 2007
CS 6710 - Digital VLSI designCS 6810 - Computer Architecture