Research Interests

Education:

• Ph.D. in Computer Science. August 2003.
  University of Rochester.
  Thesis: "Dynamic Management of Microarchitecture Resources in Future Microprocessors"
  Advisor: Dr. Sandhya Dwarkadas
  The dissertation explores the applicability of run-time adaptation to various processor structures and demonstrates that this approach serves as an effective solution to the problem of a static design that is sub-optimal for most program phases that run on it.
• M.S. in Computer Science. May 2000.
  University of Rochester.
• B.Tech in Computer Science and Engineering. July 1998.
  Indian Institute of Technology, Bombay.

Honors

• Best paper award at the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT-19) for the paper Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers , Manu Awasthi, David Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis.
• HPCA 2010 paper selected to appear in IEEE Micro's Special Issue on Top Picks from 2010 Computer Architecture Conferences.
• Best paper award at the 16th International Conference on High Performance Computing (HiPC 2009) for the paper Non-Uniform Power Access in Large Caches with Low-Swing Wires , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian.
• Research on large cache modeling (work appearing in ISCA-34 and MICRO-40 papers) selected to appear in IEEE Micro's Special Issue on Top Picks from 2007 Computer Architecture Conferences. This work is one of ten papers recognized as "the year's most significant research publications in Computer Architecture based on novelty and industry relevance".
• NSF Faculty Early Career Development Award (CAREER), 2006.
• Outstanding Teaching Award 2005, School of Computing, University of Utah.
• Dean's teaching commendation letter for CS 7968 Parallel Computer Architecture (Spring 2005) and CS/ECE 6810 Computer Architecture (Fall 2005 and Fall 2008) for student teaching evaluation ratings among the top 15% in the College of Engineering.
• IBM Ph.D. Fellowship, 2002-2003.
• University of Rochester Sproull Fellowship, 1998-2000, awarded to 10 incoming graduate students across the University.

Funding

• NSF-REU Supplement for NSF Award CCF-0916436, Rajeev Balasubramonian (PI), Mary Hall, $16,000, May 2011.
• Student travel grant awards for ISPASS 2011 ($5,000) and ISCA 2011 ($15,000) conferences (NSF).
• "Meeting Datacenter Demands with Novel DRAM Architectures", Rajeev Balasubramonian (PI), HP Labs Innovation Research Program award, $75,000 per year, August 2010 - July 2012. Press Release 2010, Press Release 2011, Press Release 2012.
• "SHF: Small: Hardware/Software Management of Large Multi-Core Memory Hierarchies", Rajeev Balasubramonian (PI), Mary Hall (co-PI), NSF Award No. CCF-0916436, $372,000, September 2009 - August 2012.
• "Formal Specification, Verification, and Test Generation for Multi-core CPUs", Ganesh Gopalakrishnan (PI), Rajeev Balasubramonian (co-PI), SRC-GRC grant, $187,291, October 2008 - September 2011.
• "CPA-CSA: Algorithms and Implementations for Scalable Transactional Memory", Rajeev Balasubramonian (PI), NSF Award No. CCF-0811249, $275,000, July 2008 - June 2011.
• "Towards Scalable Transactional Memory", Rajeev Balasubramonian (PI), Ganesh Gopalakrishnan (co-PI), University of Utah Seed Grant, $30,000, Jan 2008 - Dec 2008.
• "Reconfiguration within Large Cache Hierarchies", Rajeev Balasubramonian (PI), Intel Corporation grant, $50,000 per year (renewable up to three years), Oct 2007 - Sept 2010.
• NSF-REU Supplement for NSF CAREER Award (project exploring Transactional Memories), Rajeev Balasubramonian, $6,000, May 2007 - April 2008.
• "CAREER: Exploring Heterogeneity Within Chip Multiprocessors", Rajeev Balasubramonian (PI), NSF CAREER Award No. CCF-0545959, $300,000, May 2006 - April 2011.
• "Exploiting Fast On-Chip Wires", Rajeev Balasubramonian (PI), Al Davis (co-PI), NSF Award No. CCF-0430063, $175,000, October 2004 - September 2007.

Publications

Refereed Conference and Journal Papers

• A Novel System Architecture for Web Scale Applications Using Lightweight CPUs and Virtualized I/O. , Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian, 19th International Symposium on High-Performance Computer Architecture (HPCA-19) (Industry Track Paper) , Shenzhen, February 2013.
• Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access , Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi Iyer, 45th International Symposium on Microarchitecture (MICRO-45) , Vancouver, December 2012.
• Optimizing Datacenter Power with Memory System Levers for Guaranteed Quality-of-Service , Kshitij Sudan, Sadagopan Srinivasan, Rajeev Balasubramonian, Ravi Iyer, 21st International Symposium on Parallel Architectures and Compilation Techniques (PACT-21) , Minneapolis, September 2012.
• LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norm Jouppi, 39th International Symposium on Computer Architecture (ISCA-39) , Portland, June 2012.
• Efficient Scrub Mechanisms for Error-Prone Emerging Memories , M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian, V. Srinivasan, 18th International Symposium on High-Performance Computer Architecture (HPCA-18) , New Orleans, February 2012.
• Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads , N. Chatterjee, N. Muralimanohar, R. Balasubramonian, A. Davis, N. Jouppi, 18th International Symposium on High-Performance Computer Architecture (HPCA-18) , New Orleans, February 2012.
• Managing Data Placement in Memory Systems with Multiple Memory Controllers , Manu Awasthi, Dave Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis, International Journal of Parallel Programming (IJPP) , Vol 40(1), February 2012.
• Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norm Jouppi, 38th International Symposium on Computer Architecture (ISCA-38) , San Jose, June 2011. CRA Research Highlight .
• CHOP: Integrating DRAM Caches for CMP Server Platforms , Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravi Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian, IEEE Micro's Special issue on Top Picks from 2010 Computer Architecture Conferences , January/February 2011.
• Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers , Manu Awasthi, David Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis, 19th International Conference on Parallel Architectures and Compilation Techniques (PACT-19) , Vienna, September 2010 (Best paper award).
• SWEL: Hardware Cache Coherence Protocols to Map Shared Data onto Shared Caches , Seth H. Pugsley, Josef Spjut, David Nellans, Rajeev Balasubramonian, 19th International Conference on Parallel Architectures and Compilation Techniques (PACT-19) , Vienna, September 2010.
• Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores , Aniruddha Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norm Jouppi, 37th International Symposium on Computer Architecture (ISCA-37) , St. Malo, France, June 2010.
• Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement , Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis, 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV) , Pittsburgh, March 2010.
• Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , Bangalore, January 2010.
• CHOP: Adaptive Filter-based DRAM Caching for CMP Server Platforms , Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravi Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , Bangalore, January 2010.
• Non-Uniform Power Access in Large Caches with Low-Swing Wires , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Conference on High Performance Computing (HiPC) , Kochi, December 2009 (Best paper award).
• OS Execution on Multi-Cores: Is Out-Sourcing Worthwhile? , David Nellans, Rajeev Balasubramonian, and Erik Brunvand, Position paper in ACM Operating System Review, Special Issue on Interaction among OS, Compilers, and Multicore Processors , April 2009.
• Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches , Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John Carter, 15th International Symposium on High-Performance Computer Architecture (HPCA-15) , Raleigh, February 2009.
• Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy , Niti Madan, Li Zhao (Intel), Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer (Intel), Srihari Makineni (Intel), Donald Newell (Intel), 15th International Symposium on High-Performance Computer Architecture (HPCA-15) , Raleigh, February 2009.
• Scalable and Reliable Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT-17) , Toronto, October 2008.
• Architecting Efficient Interconnects for Large Caches with CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), selected to appear in IEEE Micro's Special issue on Top Picks from 2007 Computer Architecture Conferences , Jan/Feb 2008.
• Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
• Leveraging 3D Technology for Improved Reliability , Niti Madan, Rajeev Balasubramonian, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
• Power Efficient Approaches to Redundant Multithreading , Niti Madan, Rajeev Balasubramonian, IEEE Transactions on Parallel and Distributed Systems (Special Issue on CMP Architectures) , Vol. 18, No. 8, pp. 1066-1079, August 2007.
• Understanding the Impact of 3D Stacked Layouts on ILP , Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian, The Journal of Instruction-Level Parallelism (JILP) , Volume 9, June 2007.
• Interconnect Design Considerations for Large NUCA Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 34th International Symposium on Computer Architecture (ISCA-34) , San Diego, June 2007.
• Leveraging Wire Properties at the Microarchitecture Level , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, IEEE Micro , Vol. 26, No. 6, November/December 2006.
• Exploring the Design Space for 3D Clustered Architectures , Manu Awasthi, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
• The Effect of Interconnect Design on the Performance of Large L2 Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
• Interconnect-Aware Coherence Protocols for Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 33rd International Symposium on Computer Architecture (ISCA-33) , Boston, June 2006.
• Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity , Naveen Muralimanohar, Karthik Ramani, and Rajeev Balasubramonian, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , Austin, March 2006.
• A Case for Increased Operating System Support in Chip Multi-Processors , David Nellans, Rajeev Balasubramonian, and Erik Brunvand, 2nd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, September 2005.
• Microarchitectural Wire Management for Performance and Power in Partitioned Architectures , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, and Venkatanand Venkatachalapathy, 11th International Symposium on High-Performance Computer Architecture (HPCA-11) , San Francisco, February 2005.
• Cluster Prefetch: Tolerating On-Chip Wire Delays in Clustered Microarchitectures , Rajeev Balasubramonian, 18th International Conference on Supercomputing (ICS-18) , Saint-Malo, June 2004.
• Dynamically Tuning Processor Resources with Adaptive Processing , D.H. Albonesi, Rajeev Balasubramonian, S.G. Dropsho, S. Dwarkadas, E.G. Friedman, M.C. Huang, V. Kursun, G. Magklis, M.L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P.W. Cook, and S.E. Schuster, IEEE Computer, Special Issue on Power-Aware Computing , Vol.36, No.12, December 2003.
• A Dynamically Tunable Memory Hierarchy , Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, IEEE Transactions on Computers , Vol. 52, No. 10, October 2003.
• Dynamically Managing the Communication-Parallelism Trade-Off in Future Clustered Processors , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 30th International Symposium on Computer Architecture (ISCA-30) , San Diego, June 2003.
• Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power , Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigoris Magklis, and Michael Scott, 11th International Conference on Parallel Architectures and Compilation Techniques (PACT) , pp. 141-152, Charlottesville, September 2002.
• Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling , Greg Semeraro, Grigoris Magklis, Rajeev Balasubramonian, David Albonesi, Sandhya Dwarkadas, and Michael Scott, 8th International Symposium on High-Performance Computer Architecture (HPCA-8), pp. 29-40, Cambridge, February 2002.
• Reducing the Complexity of the Register File in Dynamic Superscalar Processors , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 34th International Symposium on Microarchitecture (MICRO-34), pp. 237-248, Austin, December 2001.
• Dynamically Allocating Processor Resources Between Nearby and Distant ILP , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 28th International Symposium on Computer Architecture (ISCA-28) , pp. 26-37, Göteborg, July 2001.
• Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, 33rd International Symposium on Microarchitecture (MICRO-33) , pp. 245-257, Monterey, December 2000.

Book and Book Chapters

• Multi-Core Cache Hierarchies , Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar, Synthesis Lectures in Computer Architecture , Morgan and Claypool Publishers, 2011.
• Buses and Crossbars , Rajeev Balasubramonian, Timothy Pinkston, Encyclopedia of Parallel Computing , D. Padua, editor. Springer Science+Business Media, 2011.

Refereed Workshop Papers and Posters

• Prediction Based DRAM Row-Buffer Management in the Many-Core Era , Manu Awasthi, David Nellans, Rajeev Balasubramonian, Al Davis, Proceedings of PACT-20 (poster session, second prize) Galveston Island, October 2011.
• Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures , Gagandeep S. Sachdev, Kshitij Sudan, Mary W. Hall, Rajeev Balasubramonian, Proceedings of PACT-20 (poster session) Galveston Island, October 2011.
• Refining the Utility Metric for Utility-Based Cache Partitioning , Xing Lin, Rajeev Balasubramonian, 9th Workshop on Duplicating, Deconstructing, and Debunking (WDDD), held in conjunction with ISCA-38, San Jose, June 2011.
• Handling PCM Resistance Drift with Device, Circuit, Architecture, and System Solutions , Manu Awasthi, Manju Shevgoor, Kshitij Sudan, Rajeev Balasubramonian, Bipin Rajendran, Viji Srinivasan, 2nd Non-Volatile Memories Workshop (NVMW), San Diego, March 2011.
• Improving Server Performance on Multi-Cores via Selective Off-loading of OS Functionality , David Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian, 6th Workshop on Interaction between Operating Systems and Computer Architecture (WIOSCA), held in conjunction with ISCA-37, St. Malo, France, June 2010.
• Rethinking DRAM Design for Low-Power Datacenters, Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, 16th International Conference on High Performance Computing (HiPC)(poster session, best poster presentation award), India, December 2009.
• Optimizing a Multi-Core Processor for Message-Passing Workloads , Niladrish Chatterjee, Seth H. Pugsley, Josef Spjut, Rajeev Balasubramonian, 5th Workshop on Unique Chips and Systems (UCAS-5), held in conjunction with ISPASS, Boston, April 2009.
• Exploiting Eager Register Release in a Redundantly Multi-Threaded Processor , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on Architectural Reliability (WAR-2), held in conjunction with MICRO-39, Orlando, December 2006.
• Leveraging Bloom Filters for Smart Search Within NUCA Caches , Robert Ricci, Steve Barrus, Dan Gebhardt, Rajeev Balasubramonian, 7th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-33 , Boston, June 2006.
• Re-Visiting the Performance Impact of Microarchitectural Floorplanning , Anupam Chakravorty, Abhishek Ranjan, Rajeev Balasubramonian, 3rd Workshop on Temperature Aware Computer Systems (TACS), held in conjunction with ISCA-33 , Boston, June 2006.
• A First-Order Analysis of Power Overheads of Redundant Multi-Threading , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on the System Effects of Logic Soft Errors (SELSE-2) , Urbana, April 2006.
• Wire Management for Coherence Traffic in Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 6th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-32 , Madison, June 2005.
• Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors , Karthik Ramani, Naveen Muralimanohar, and Rajeev Balasubramonian, 5th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-31 , Munich, June 2004.
• Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches , Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, and Alper Buyuktosunoglu, 3rd Workshop on Power-Aware Computer Systems (PACS), held in conjunction with MICRO-36 , San Diego, December 2003.
• Dynamic Memory Hierarchy Performance Optimization , Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, Workshop on Solving the Memory Wall Problem , held in conjunction with the 27th ISCA, Vancouver, June 2000.

Non-Refereed Publications

• USIMM: the Utah SImulated Memory Module , Niladrish Chatterjee, Rajeev Balasubramonian, Manjunath Shevgoor, Seth H. Pugsley, Aniruddha N. Udipi, Ali Shafiee, Kshitij Sudan, Manu Awasthi, Zeshan Chishti, Technical Report UUCS-12-002, February 2012.
• Interference Aware Cache Designs for Operating System Execution , David Nellans, Rajeev Balasubramonian, and Erik Brunvand, Technical Report UUCS-09-002, February 2009.
• Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, Technical Report UUCS-08-001, January 2008.
• Commit Algorithms for Scalable Hardware Transactional Memory , Seth H. Pugsley, Rajeev Balasubramonian, Technical Report UUCS-07-016, August 2007.
• Power-Efficient Approaches to Reliability , Niti Madan, Rajeev Balasubramonian, Technical Report UUCS-05-010, December 2005.
• Dynamic Management of Microarchitecture Resources in Future Microprocessors , Rajeev Balasubramonian, Ph.D. Thesis, Department of Computer Science, University of Rochester, August 2003.
• Microarchitectural Trade-offs in the Design of a Scalable Clustered Microprocessor , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, URCS Technical Report #771, January 2002.
• A High-Performance Two-Level Register File Organization , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, URCS Technical Report #745, Apr 2001.
• Dynamically Allocating Processor Resources between Nearby and Distant ILP , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, URCS Technical Report #743, Apr 2001.

Patents

• A Heterogeneous Architecture for Reliable, High-Endurance Memory Systems, patent pending (filed 6/2011).
• A Slot-based Memory Interface with Single-Point Arbitration and Simplified Memory Controllers, patent pending (filed 3/2011).
• Memory Access Methods and Apparatus, patent pending (filed 1/2010).
• Performance Monitoring for New Phase Dynamic Optimization of Instruction Dispatch Cluster Configuration, Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, US Patent No. 8,103,856, issued Jan 24 2012.
• Multi-Cluster Processor Operating only Select Number of Clusters during each Phase Based on Program Statistic Monitored at Predetermined Intervals, Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, US Patent No. 7,490,220, issued Feb 10 2009.
• Microarchitectural Wire Management for Performance and Power in Partitioned Architectures, R. Balasubramonian, L. Cheng, J. Carter, N. Muralimanohar, K. Ramani, US Patent No. 7,478,190, issued Jan 13 2009.
• Multiple Clock Domain Microprocessor, David H. Albonesi, Greg Semeraro, Grigoris Magklis, Michael L. Scott, Rajeev Balasubramonian, and Sandhya Dwarkadas, US Patent No. 7,089,443, issued Aug 8 2006.
• Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, US Patent No. 6,834,328, issued Dec 21 2004.
• Dynamically Reconfigurable Memory Hierarchy, Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, US Patent No. 6,684,298, issued Jan 27 2004.

Teaching

• Spring 2011: CS 7810: Advanced Computer Architecture.
• Spring 2011: CS 7940: Architecture/Async Reading Seminar.
• Fall 2010: CS/EE 6810 Computer Architecture
• Fall 2010: CS 7937 Architecture/Async Reading Seminar
• Spring 2009: CS 7810/ CS 7960: Advanced Computer Architecture.
• Spring 2009: CS 7940-10: Architecture/Async Reading Seminar.
• Fall 2008: CS/EE 6810 Computer Architecture
• Fall 2008: CS 7937 Architecture/Async Reading Seminar
• Spring 2008: CS 7820: Parallel Computer Architecture.
• Spring 2008: CS 7940-10: Architecture/Async Reading Seminar.
• Fall 2007: CS/EE 6810 Computer Architecture
• Fall 2007: CS 7937 Architecture/Async Reading Seminar
• Spring 2007: CS 7820: Parallel Computer Architecture.
• Spring 2007: CS 7940-10: Architecture/Async Reading Seminar.
• Fall 2006: CS/EE 3810 Computer Organization
• Fall 2006: CS 7937 Architecture/Async Reading Seminar
• Spring 2006: CS/EE 7810 Advanced Computer Architecture
• Spring 2006: CS 7940-10: Architecture/Async Reading Seminar.
• Fall 2005: CS/EE 6810 Computer Architecture
• Fall 2005: CS 7937 Architecture/Async Reading Seminar
• Spring 2005: CS 7968: Parallel Computer Architecture.
• Spring 2005: CS 7940-10: Architecture/Async Reading Seminar.
• Fall 2004: CS/EE 5810/6810 Advanced Computer Architecture
• Fall 2004: CS 7940-08 Architecture/Async Reading Seminar
• Spring 2004: CS 7960-4: Special Topics in High-Performance Architectures.
• Spring 2004: CS 7940-10: Architecture/Async Reading Seminar.
  

Students

Graduated:

• Naveen Muralimanohar , Ph.D. September 2008, Wire-Aware Cache Architectures , First employment: HP Labs.
• Niti Madan , Ph.D. January 2009, Leveraging Mixed-process 3D Die Stacking Technology for Cache Hierarchies and Reliability , First employment: Computing Innovation Fellow at IBM T.J. Watson, Current employment: Oracle.
• Manu Awasthi , Ph.D. September 2011, Managing Data Locality in Future Memory Hierarchies Using a Hardware Software Co-Design Approach , First employment: Micron.
• Aniruddha Udipi , Ph.D. March 2012, Designing Efficient Memory for Future Computing Systems , First employment: ARM.
• Kshitij Sudan , Ph.D. October 2012, Data Placement in Modern Memory Systems , First employment: Samsung.
• Vivek Venkatesan , M.S. December 2007, Criticality of On-Chip Wires , First employment: Sun (currently, Oracle).

Current:

• Niladrish Chatterjee , Ph.D. student, Memory Scheduling
• Seth Pugsley (brace yourself... this link has stunning graphics and Flash) , Ph.D. student, Processing Near Memory
• Manju Shevgoor , Ph.D. student, Memory Systems
• Ali Shafiee , Ph.D. student, Memory Systems
• Co-advising Dave Nellans , Ph.D. student, Optimizing OS Execution
• Byong Wu Chong, M.S. student, Transactional Memory

Talks

Service

• Program Chair, ISPASS 2011
• General Chair, ISPASS 2012
• Workshop Co-Chair:
  • 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3), Memory Scheduling Championship (MSC) , co-located with ISCA 2012.
  • 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI) , co-located with HPCA 2010.
  • 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI) , co-located with ISCA 2009.
  • 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI) , co-located with ISCA 2008.
• Program committee member: ISPASS 2006 , ISPASS 2007 , HiPC 2007 , HPCA 2008 , ICPP 2008 , HiPC 2008 , MICRO 2008 , dasCMP 2008 , NOCS 2009 , 3D Workshop 2009 , UCAS 2009 , HiPC 2009 , NOCS 2010 , HiPC 2010 , IISWC 2010 , UCAS 2010 , WRA 2010 , HPCA 2011 , NOCS 2011 , IEEE Micro Top Picks 2010 , MICRO 2011 , HiPC 2011 , HiPEAC 2012 , ISCA 2012 , NOCS 2012 , ICPP 2012 , MSPC 2012 , HiPEAC 2013 , ISPASS 2013 , NSF panels (2005, 2006, 2008, 2008, 2011), DOE panel (2010).
• Finance chair: ISCA 2011 , HPCA 2013.
• Student Travel Chair: ISCA 2013 .
• ACM Student Research Competition Chair: PACT 2012 .
• Registration chair: ISPASS 2007 , HPCA 2008 , ISPASS 2008 , ISPASS 2009 , HPCA 2010 .
• External Review Committee for ISCA 2010 , ASPLOS 2012 .
• Reviewer for numerous conferences and journals.
• Invited participant at NSF-sponsored workshops: OCIN 2006 , WETI 2012 , CPOM 2012 .
• Organizer, Multi-Core Colloquium , School of Computing, University of Utah, Fall 2007.
• School of Computing ABET Co-ordinator, Computer Engineering program, 2007-2009.
• Member of the University of Utah, College of Engineering Council, 2005-2007.
• Graduate admissions committee (School of Computing), 2003-2009.
• Curriculum committee, 2010-2012.
• Graduate admissions chair (School of Computing), 2010-2012.

Contact Information: