Curriculum Vitae

Rajeev Balasubramonian
Professor
School of Computing
University of Utah


Research Interests

Computer architecture and systems: DRAM and NVM main memory systems, memory reliability, memory architectures for big-data workloads, large cache hierarchies, on- and off-chip interconnects, transactional memory.


Education


Employment


Awards


Funding


Publications

Refereed Conference and Journal Papers

Book and Book Chapters

Refereed Workshop Papers and Posters

Non-Refereed Publications


Patents


Teaching


Students

Graduated:

Current:


Talks

Invited seminars at IIT, Bombay (Jan 2001), University of Minnesota (Feb 2003), University of Southern California (Feb 2003), University of Utah (Mar 2003), Georgia Tech (Mar 2003), IBM T.J. Watson (Apr 2003), University of Massachusetts (Apr 2003), Washington University (Apr 2003), University of Rochester (Sept 2007), Cornell University (Sept 2007), Princeton University (Oct 2007), BYU (Oct 2007), Harvard University (Feb 2010), Intel (March 2011), Micron (May 2011), IBM (October 2012), Intel (September 2013), HP Labs (January 2014), CMU (April 2014), CMU Cloud Workshop (April 2014), University of Edinburgh (May 2014), D43D (Design for 3D) Workshop at EPFL (June 2014).

Presented papers at the Memory Wall Workshop (June 2000), MICRO-33 (Dec 2000), ISCA-28 (July 2001), MICRO-34 (Dec 2001), ISCA-30 (June 2003), Power-Aware Computer Systems Workshop (Dec 2003), ICS-18 (June 2004), and HPCA-19 (Feb 2013).


Service


Contact Information:

Email : rajeev
Address : 50 S. Central Campus Drive, Rm. 3190, Salt Lake City, UT 84112
Office Phone : 801-581-4553