Research

Rajeev Balasubramonian

My research focuses on many aspects of computer architecture. I am especially interested in studying how future technology trends influence the design of microprocessors. Current and past projects are listed below . Current areas of focus:

• Memory Systems : optimizing memory controller and DRAM behavior for high performance and low energy.
• Interconnect design : leveraging different wires in a heterogeneous network for architectural innovation.
• Large cache design : methodologies to model large NUCA cache hierarchies, policies to organize data, reconfiguration within the hierarchy, on-chip network innovations, organizations in 3D.
• Transactional memory : innovations for scalable hardware transactional memory.
• Reliability : efficient verification of on-chip computation and communication.

As a graduate student, I delved into problems involving memory hierarchy bottlenecks ( MICRO'00 ), pre-execution threads ( ISCA'01 ), register file complexity ( MICRO'01 ), and scalability of clustered microprocessors ( ISCA'03 ). Ph.D. Thesis.

Full publication list (in chronological order)

Students

Graduated:

• Naveen Muralimanohar , Ph.D. September 2008, Wire-Aware Cache Architecture , First employment: HP Labs
• Niti Madan , Ph.D. January 2009, Leveraging Mixed-process 3D Die Stacking Technology for Cache Hierarchies and Reliability , First employment: Computing Innovation Fellow at IBM T.J. Watson
• Vivek Venkatesan , M.S. December 2007, Criticality of On-Chip Wires , First employment: Sun

Current:

• Manu Awasthi , Ph.D. student, Memory Controller Design
• Kshitij Sudan , Ph.D. student, Memory Hierarchies
• Aniruddha Udipi , Ph.D. student, Scalable Interconnects
• Seth Pugsley, Ph.D. student, Cache Coherence
• Niladrish Chatterjee , Ph.D. student, Customization for MPI Workloads
• Byong Wu Chong, M.S. student, Transactional Memory
• Co-advising Dave Nellans , Ph.D. student, Optimizing OS Execution

Software Release

CACTI 6.0

Research projects and corresponding publications

• Memory Systems.

  Modern multi-core processors are placing severe pressure on DRAM main memory systems. Several opportunities for innovation exist: better scheduling policies within multiple memory controllers, increasing the utilization of DRAM row buffers, reducing energy dissipated per DRAM access, QoS guarantees within the memory system, etc.
  
  
  • Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement , Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis, 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV) , Pittsburgh, March 2010.
  
  
  

• Design of Large Cache Hierarchies.

  More than half the area of future chips will be occupied by large cache hierarchies. Large caches will be partitioned into numerous banks connected by an on-chip network -- a non-uniform cache architecture (NUCA). On-going work is designing tools to estimate an optimal cache organization and exploring mechanisms (reconfiguration, data mapping, on-chip network design) to improve a core's access to its data.
  
  
  • Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , Bangalore, January 2010.
  • CHOP: Adaptive Filter-based DRAM Caching for CMP Server Platforms , Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravi Iyer, Srihari Makineni, Zhen Fang, Donald Newell, Yan Solihin, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , Bangalore, January 2010.
  • Non-Uniform Power Access in Large Caches with Low-Swing Wires , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Conference on High Performance Computing (HiPC) , Kochi, December 2009 (Best paper award).
  • Optimizing a Multi-Core Processor for Message-Passing Workloads , Niladrish Chatterjee, Seth H. Pugsley, Josef Spjut, Rajeev Balasubramonian, 5th Workshop on Unique Chips and Systems (UCAS-5), held in conjunction with ISPASS, Boston, April 2009.
  • Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches , Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John Carter, 15th International Symposium on High-Performance Computer Architecture (HPCA-15) , Raleigh, February 2009.
  • Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy , Niti Madan, Li Zhao (Intel), Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer (Intel), Srihari Makineni (Intel), Donald Newell (Intel), 15th International Symposium on High-Performance Computer Architecture (HPCA-15) , Raleigh, February 2009.
  • Architecting Efficient Interconnects for Large Caches with CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), selected to appear in IEEE Micro's Special issue on Top Picks from 2007 Computer Architecture Conferences , Jan/Feb 2008.
  • Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
  • Interconnect Design Considerations for Large NUCA Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 34th International Symposium on Computer Architecture (ISCA-34) , San Diego, June 2007.
  • The Effect of Interconnect Design on the Performance of Large L2 Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
  • Leveraging Bloom Filters for Smart Search Within NUCA Caches , Robert Ricci, Steve Barrus, Dan Gebhardt, Rajeev Balasubramonian, 7th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-33 , Boston, June 2006.
  • A Dynamically Tunable Memory Hierarchy , Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, IEEE Transactions on Computers, Vol.52, No.10, October 2003.
  
  
  

• Managing Wires at the Architecture Level.

  In future architectures, computation will be relatively cheap, while communication will be expensive. Performance can be degraded by wires that take tens of cycles to send signals across the length of the chip. Interconnects also contribute a significant fraction of power dissipated in modern processors. VLSI techniques enable a variety of wire implementations with different latency, power, and bandwidth properties. This project is examining if power and performance bottlenecks can be alleviated by exposing wire properties to the architecture level.
  
  
  • Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , Bangalore, January 2010.
  • Non-Uniform Power Access in Large Caches with Low-Swing Wires , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Conference on High Performance Computing (HiPC) , Kochi, December 2009 (Best paper award).
  • Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy , Niti Madan, Li Zhao (Intel), Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer (Intel), Srihari Makineni (Intel), Donald Newell (Intel), 15th International Symposium on High-Performance Computer Architecture (HPCA-15) , Raleigh, February 2009.
  • Architecting Efficient Interconnects for Large Caches with CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), selected to appear in IEEE Micro's Special issue on Top Picks from 2007 Computer Architecture Conferences , Jan/Feb 2008.
  • Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
  • Understanding the Impact of 3D Stacked Layouts on ILP , Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian, The Journal of Instruction-Level Parallelism (JILP) , Volume 9, June 2007.
  • Interconnect Design Considerations for Large NUCA Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 34th International Symposium on Computer Architecture (ISCA-34) , San Diego, June 2007.
  • Leveraging Wire Properties at the Microarchitecture Level , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, IEEE Micro , Vol. 26, No. 6, November/December 2006.
  • Exploring the Design Space for 3D Clustered Architectures , Manu Awasthi, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
  • The Effect of Interconnect Design on the Performance of Large L2 Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
  • Interconnect-Aware Coherence Protocols for Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 33rd International Symposium on Computer Architecture (ISCA-33) , Boston, June 2006.
  • Re-Visiting the Performance Impact of Microarchitectural Floorplanning , Anupam Chakravorty, Abhishek Ranjan, Rajeev Balasubramonian, 3rd Workshop on Temperature Aware Computer Systems (TACS), held in conjunction with ISCA-33 , Boston, June 2006.
  • Wire Management for Coherence Traffic in Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 6th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-32 , Madison, June 2005.
  • Microarchitectural Wire Management for Performance and Power in Partitioned Architectures , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, and Venkatanand Venkatachalapathy, 11th International Symposium on High-Performance Computer Architecture (HPCA-11) , San Francisco, February 2005.
  • Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors , Karthik Ramani, Naveen Muralimanohar, and Rajeev Balasubramonian, 5th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-31 , Munich, June 2004.
  • Microarchitectural Wire Management for Performance and Power in Partitioned Architectures, R. Balasubramonian, L. Cheng, J. Carter, N. Muralimanohar, K. Ramani, US Patent No. 7,478,190, issued Jan 13 2009.
  
  
  

• Power-Efficient Reliability.

  Radiation and noise-induced transient errors in computer systems are on the rise. Such errors can be detected at the architecture level by executing two copies of every instruction and conducting periodic checks. This technique is commonly referred to as redundant multi-threading (RMT). However, it can impose significant power overheads. This project is attempting a comprehensive analysis of RMT techniques to better understand how we can simultaneously optimize reliability, power, and performance.
  
  
  • Leveraging 3D Technology for Improved Reliability , Niti Madan, Rajeev Balasubramonian, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
  • Power Efficient Approaches to Redundant Multithreading , Niti Madan, Rajeev Balasubramonian, IEEE Transactions on Parallel and Distributed Systems (Special Issue on CMP Architectures) , Vol. 18, No. 8, pp. 1066-1079, August 2007.
  • Exploiting Eager Register Release in a Redundantly Multi-Threaded Processor , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on Architectural Reliability (WAR-2), held in conjunction with MICRO-39, Orlando, December 2006.
  • A First-Order Analysis of Power Overheads of Redundant Multi-Threading , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on the System Effects of Logic Soft Errors (SELSE-2) , Urbana, April 2006.
  • Power-Efficient Approaches to Reliability , Niti Madan, Rajeev Balasubramonian, Technical Report UUCS-05-010, December 2005.
  
  
  

• Transactional Memory.

  Transactional memory (TM) is viewed as a promising approach to simplify the task of parallel programming. It is widely believed that support for TM can be provided by the hardware and many implementation flavors have been recently proposed. We are currently exploring scalability, power-efficiency, and verification aspects of these implementations.
  
  
  • Scalable and Reliable Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT-17) , Toronto, October 2008.
  • Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, Technical Report UUCS-08-001, January 2008.
  • Commit Algorithms for Scalable Hardware Transactional Memory , Seth H. Pugsley, Rajeev Balasubramonian, Technical Report UUCS-07-016, August 2007.
  
  
  

• Scalability of Clustered Microarchitectures.

  Clustered microarchitectures distribute the processor's resources across multiple clusters. Because of the small size of each individual cluster, complexity is lower and a faster clock is possible. Instructions and data of a single program are distributed across the clusters, incurring frequent data communications and an IPC penalty. The increased cost of wire delays in future generations renders microprocessors communication-bound. This project examines many performance and power issues in the design of highly clustered microarchitectures at future technology points.
  
  
  • Understanding the Impact of 3D Stacked Layouts on ILP , Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian, The Journal of Instruction-Level Parallelism (JILP) , Volume 9, June 2007.
  • Exploring the Design Space for 3D Clustered Architectures , Manu Awasthi, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
  • Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity , Naveen Muralimanohar, Karthik Ramani, and Rajeev Balasubramonian, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , Austin, March 2006.
  • Cluster Prefetch: Tolerating On-Chip Wire Delays in Clustered Microarchitectures , Rajeev Balasubramonian, 18th International Conference on Supercomputing (ICS-18) , Saint-Malo, June 2004.
  • Dynamically Managing the Communication-Parallelism Trade-Off in Future Clustered Processors , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 30th International Symposium on Computer Architecture (ISCA-30), San Diego, June 2003.
  • Microarchitectural Trade-offs in the Design of a Scalable Clustered Microprocessor , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, URCS Technical Report #771, January 2002.
  • Multi-Cluster Processor Operating only Select Number of Clusters during each Phase Based on Program Statistic Monitored at Predetermined Intervals, Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, US Patent No. 7,490,220, issued Feb 10 2009.
  
  
  

• Exploiting Criticality for Low Power Cache Design.

  Most low power techniques for the data cache introduce access time penalties. We propose the use of two cache banks, one optimized for high performance, and the other optimized for low power. Instructions and data are split into two streams, and instructions that lie on the program critical path are steered to the high performance cache so that the performance impact of the low power cache is kept to a minimum.
  
  
  • Non-Uniform Power Access in Large Caches with Low-Swing Wires , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Conference on High Performance Computing (HiPC) , Kochi, December 2009 (Best paper award).
  • Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches , Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu, 3rd Workshop on Power-Aware Computer Systems (PACS), held in conjunction with MICRO-36 , San Diego, December 2003.
  
  
  

• Dynamic Voltage and Frequency Scaling.

  Problems with clock distribution and wire delays motivate the use of multiple domains within the processor, each with its own clock. This provides the opportunity to scale down the frequency and voltage of each individual domain in order to reduce energy consumption. By only targeting those domains that do not lie on the critical path for the program, the impact on performance is minimized.
  
  
  
  • Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling , Greg Semeraro, Grigoris Magklis, Rajeev Balasubramonian, David Albonesi, Sandhya Dwarkadas, and Michael Scott, 8th International Symposium on High-Performance Computer Architecture (HPCA-8), pp. 29-40, Cambridge, February 2002.
  • Multiple Clock Domain Microprocessor, David H. Albonesi, Greg Semeraro, Grigoris Magklis, Michael L. Scott, Rajeev Balasubramonian, and Sandhya Dwarkadas, US Patent No. 7,089,443, issued Aug 8 2006.
  
  
  

• Register File Complexity.

  The number of registers and register ports dictate the amount of ILP that can be extracted. At the same time, the access time and the energy consumption of the register file pose serious design constraints. We evaluate the effect of two orthogonal techniques on performance, energy, and cycle time. The first splits the register file into two levels to reduce the number of entries in the first level. The second introduces scheduling complexity in the issue queue and at the functional units in order to reduce the porting requirements on the register file.
  
  
  
  • Exploiting Eager Register Release in a Redundantly Multi-Threaded Processor , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on Architectural Reliability (WAR-2), held in conjunction with MICRO-39, Orlando, December 2006.
  • Reducing the Complexity of the Register File in Dynamic Superscalar Processors , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 34th International Symposium on Microarchitecture (MICRO-34), pp. 237-248, Austin, December 2001.
  • A High-Performance Two-Level Register File Organization , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, URCS Technical Report #745, Apr 2001.
  
  
  

• Efficient Pre-Execution Threads.

  The ability to mine distant ILP is hampered by the limited size of the register file, a key determinant of cycle time. This work proposes the use of a helper thread that uses part of the register file to jump ahead of the processor state to prefetch data and resolve branch predictions early. The helper thread can look in a much larger window for ILP because of relaxed conditions for register deallocation. A runtime scheme dynamically determines the partition of resources between the main program thread and the pre-execution thread.
  
  
  
  • Dynamically Allocating Processor Resources Between Nearby and Distant ILP , Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, 28th International Symposium on Computer Architecture (ISCA-28), pp. 26-37, Göteborg, July 2001.
  • A more comprehensive version of the same paper appears as URCS Technical Report #743 .
  
  
  

• Reconfigurable Memory Hierarchies.

  This work explores the potential of a novel cache and TLB layout that allows for low-cost configurability. The boundary between the L1 and L2 can be dynamically changed so that each program phase is given the amount of L1 that has the best capacity/access time trade-off. In addition to improving performance, this also helps reduce energy consumption by reducing the number of transfers between the various levels of the hierarchy.
  
  
  
  • Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, 33rd International Symposium on Microarchitecture (MICRO-33), pp. 245-257, Monterey, December 2000.
  • A Dynamically Tunable Memory Hierarchy , Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, IEEE Transactions on Computers, Vol.52, No.10, October 2003.
  • Dynamically Tuning Processor Resources with Adaptive Processing , D.H. Albonesi, Rajeev Balasubramonian, S.G. Dropsho, S. Dwarkadas, E.G. Friedman, M.C. Huang, V. Kursun, G. Magklis, M.L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P.W. Cook, S.E. Schuster, IEEE Computer, Special Issue on Power-Aware Computing , Vol.36, No.12, December 2003.
  • Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power , Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigoris Magklis, and Michael Scott, 11th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 141-152, Charlottesville, September 2002.
  • Dynamic Memory Hierarchy Performance Optimization , Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, Workshop on Solving the Memory Wall Problem, held in conjunction with the 27th ISCA, Vancouver, June 2000.
  • Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, US Patent No. 6,834,328, issued Dec 21 2004.
  • Dynamically Reconfigurable Memory Hierarchy, Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, and Sandhya Dwarkadas, US Patent No. 6,684,298, issued Jan 27 2004.