Improving Direct-Mapped Cache Performance by the Addition of a Small 
Fully-Associative Cache and Prefetch Buffers

Q1. How many sets are there in a 16KB 2-way cache with a 32-byte line size?
    If the address has 64 bits, how many bits are stored in the cache's tag
    array? :-)

Q2. Suggest additional ways to improve the performance of stream buffers.

Q3. What are your thoughts on the usefulness of victim caches and stream
    buffers for L1 and L2 caches (instruction and data) for high-performance
    processors in 2005?