Fall 2007: CS/EE 6810 Computer Architecture
General Information:
- Venue: MEB 3105
- Time: Tuesday, Thursday 9:10am - 10:30am
- Instructor: Rajeev Balasubramonian, email: rajeev, MEB 3124, office hours: by appointment
- Pre-Requisite: CS 3810 or equivalent
- TA: Avishek Saha (email: avishek@cs)(office hours: Mon-Wed 2-3pm)(office: MEB 3421);
Vivek Venkatesan (email: vvenkate@cs)(office hours: Mon 3-4pm)(office: MEB 2162)
- Textbook: Computer Architecture A Quantitative Approach - 4th Edition, John Hennessy and David Patterson
- Class mailing list: cs6810@cs.utah.edu. Visit the mailman system to sign up or modify.
Prerequisites:
You are expected to know introductory computer architecture concepts,
such as those covered in CS 3810 (textbook for 3810: Computer Organization
and Design, Patterson and Hennessy, 4th edition). You will be well-served
to re-visit some of the basic concepts in the 3810 textbook before the
first day of class.
College of Engineering Add/Drop Policy:
Guidelines from the college.
Special Needs:
The University of Utah seeks to provide equal access to its programs,
services and activities for people with disabilities. If you will
need accommodations in the class, reasonable prior notice needs to be
given to the Center for Disability Services, 162 Olpin Union Building,
581-5020 (V/TDD). CDS will work with you and the instructor to make
arrangements for accommodations.
All written information in this course can be made available in
alternative format with prior notification to the Center for
Disability Services.
Grading:
The following is a tentative guideline and may undergo changes.
Two mid-term exams will count for 50% of the final grade.
The remaining 50% will be based on homework assignments.
We have zero tolerance for cheating -- if your class rank in the
assignments is significantly different from your class rank in
the exams, only your rank in the exams will count towards your
grade. We know you're juggling multiple activities and the
assignment deadline may not always be favorable. You are
therefore allowed to skip one of the assignments -- use
this freebie prudently. Late submissions will not be graded.
Class Schedule
Read the relevant sections in the textbook *before* the lecture.
Chapter 1: Quantitative Metrics
- Tu 21st Aug:
Logistics and introduction. Quantifying computer performance.
Reading: review the pre-req textbook for CS 3810: Computer Organization and Design, Patterson and Hennessy.
Reading: 6810 textbook: Sections 1.1, 1.4, 1.5, 1.8.
Slides:
(powerpoint)
(pdf)
- Th 23rd Aug:
System Metrics and Pipelining.
Reading: Sections 1.6, 1.7, 1.9, A.1.
Homework: #1 handed out .
Slides:
(powerpoint)
(pdf)
- Tu 28th Aug:
Pipelining basics.
Reading: Sections A.1-A.3.
Slides:
(powerpoint)
(pdf)
- Th 30th Aug:
Advanced pipelining.
Reading: Sections A.4-A.10.
Slides:
(powerpoint)
(pdf)
- Tu 4th Sept:
Software ILP basics.
Reading: Sections 2.1-2.2.
Homework: #1 due.
Homework: #2 handed out .
Slides:
(powerpoint)
(pdf)
- Th 6th Sept:
More software ILP.
Reading: Section 2.2, Appendix G.
Slides:
(powerpoint)
(pdf)
- Tu 11th Sept:
Static speculation and branch prediction.
Reading: Appendix G, Section 2.3.
Homework: #2 due.
Slides:
(powerpoint)
(pdf)
- Th 13th Sept:
Branch prediction, Out-of-order processors.
Reading: Sections 2.3-2.6.
Homework: #3 handed out .
Slides:
(powerpoint)
(pdf)
- Tu 18th Sept:
More Dynamic ILP.
Reading: Sections 2.3-2.6.
Detailed Notes on Out-of-order execution
Slides:
(powerpoint)
(pdf)
- Th 20th Sept:
ILP innovations.
Reading: None.
Slides:
(powerpoint)
(pdf)
- Tu 25th Sept:
No Class
- Th 27th Sept:
SMT and Cache basics.
Reading: Sections 3.5, 5.1, Appendix C.1-C.3.
Homework: #3 due.
Homework: #4 handed out .
Slides:
(powerpoint)
(pdf)
- Tu 2nd Oct:
Cache innovations.
Reading: Section 5.2.
Slides:
(powerpoint)
(pdf)
- Th 4th Oct:
Main memory and Virtual memory issues.
Reading: Section 5.3 and Appendix C.4-C.5.
Homework: #4 due.
Slides:
(powerpoint)
(pdf)
- Tu 9th Oct:
Fall Break.
- Th 11th Oct:
Fall Break.
- Tu 16th Oct:
Virtual memory issues.
Reading: Sections 5.4-5.8.
Slides:
(powerpoint)
(pdf)
- Th 18th Oct:
Mid-Term Exam (open book, open notes), based on Chapters 1-3 and Appendix A.
Homework: #5 handed out .
- Tu 23rd Oct:
Large cache design.
Reading: None.
Slides:
(powerpoint)
(pdf)
- Th 25th Oct:
Cache innovations, Processor case studies.
Reading: Section 5.2.
Slides:
(powerpoint)
(pdf)
- Tu 30th Oct:
Multiprocessor intro.
Reading: Section 4.1.-4.2.
Slides:
(powerpoint)
(pdf)
- Th 1st Nov:
Symmetric shared-memory architectures.
Reading: Section 4.2.-4.4.
Homework: #5 due.
Slides:
(powerpoint)
(pdf)
- Tu 6th Nov:
Distributed shared-memory architectures and Synchronization.
Reading: Section 4.4.-4.5.
Homework: #6 handed out .
Slides:
(powerpoint)
(pdf)
- Th 8th Nov:
Consistency models.
Reading: Section 4.6.
Reading: Section 4.7.-4.10.
Slides:
(powerpoint)
(pdf)
- Tu 13th Nov:
Advanced multi-core topics (Transactional Memory).
Slides:
(powerpoint)
(pdf)
- Th 15th Nov:
Transactional Memory.
Homework: #6 due.
Homework: #7 handed out .
Slides:
(powerpoint)
(pdf)
- Tu 20th Nov:
Interconnection network basics.
Reading: Appendix E.
Slides:
(powerpoint)
(pdf)
- Th 22nd Nov:
Thanksgiving break.
- Tu 27th Nov:
Interconnection networks.
Reading: None
Slides:
(powerpoint)
(pdf)
- Th 29th Nov:
Interconnection networks.
Reading: None
Homework: #7 due.
Slides:
(powerpoint)
(pdf)
- Tu 4th Dec:
2nd Mid-Term Exam (open book, open notes), based primarily on Caches, Multiprocessors, Transactional Memory, Interconnection Networks.
- Th 6th Dec:
Wrap-up.
Slides:
(powerpoint)
(pdf)