Assignment 9

Due: 9:10am, at the start of class, Tue Dec 5th, 2006

Note: Make reasonable assumptions where necessary and clearly state them. Each of the 3 problems is worth an equal number of points. Feel free to discuss problems with classmates, but the only written material that you may consult while writing your solutions are the textbook and lecture slides.

You may hand in solutions on paper at the start of class. You may also hand in homeworks electronically on one of the CADE Lab machines. Place your solution in a text file called "homework9" (if you use a different file name, our print script may not find it) and use the following command:
handin cs3810 hw9 homework9

1. Consider a 4-processor multiprocessor that has the following properties: (i) uniform memory-access organization, (ii) snooping-based MSI cache coherence protocol, (iii) write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. Show the states of the block X in each of the four caches after every operation below.
   • P1: Write X
   • P1: Write X
   • P2: Read X
   • P3: Read X
   • P4: Write X
2. Consider a 4-processor multiprocessor that has the following properties: (i) non-uniform memory-access organization, (ii) directory-based cache coherence protocol, (iii) write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. Assume that data X is stored in the local memory of processor P2. Describe the information stored in the directory for data X after every operation below.
   • P1: Write X
   • P1: Write X
   • P2: Read X
   • P3: Read X
   • P4: Write X
3. For the multiprocessor system in problem 1, assume that the coherence protocol employs the following messages: (i) Request message (address and request type), (ii) Data message. For each of the five operations in problem 1, specify the corresponding number of request and data messages required on the bus.