Email: my first name @ cs.utah.edu
50 S. Central Campus Drive, Rm. 3414,
Salt Lake City, UT 84112
Ph: 801-581-4553; Fax: 801-581-5843
Detailed research page |
Full publication list |
Teaching page |
Utah Arch Research Group |
- ACM SIGARCH Blog Editor.
- Book: Innovations in the Memory System.
- HPCA 2019 Program Co-Chair.
- Tutorial on Runtimes in the Cloud , 2018, 2019, 2020.
- IEEE Micro Special Issue on Near Data Processing , guest co-editor, Jan/Feb 2016.
- 3rd Workshop on Near-Data Processing , co-located with MICRO 2015.
- 2nd Workshop on Near-Data Processing , co-located with MICRO 2014.
- The Memory Forum , co-located with ISCA 2014.
- ASPLOS 2014
- 1st Workshop on Near-Data Processing , co-located with MICRO 2013.
- JWAC Memory Scheduling Championship at ISCA 2012, based on the USIMM memory system simulation infrastructure.
- Book: Multi-Core Cache Hierarchies.
Recent Papers (Full list of publications) :
Other Selected Publications (Full list of publications) :
My research focuses on many aspects of computer architecture. I am
especially interested in studying how future technology trends
influence the design of microprocessors and memory systems. In recent
years, we have focused on designing memory systems that can cater to
the bandwidth, latency, power, cost, security, and reliability demands of
datacenter and big-data workloads. We are also exploring neuromorphic
Current projects include:
Past projects include:
- Neuromorphic Architectures : designing accelerators and biology-inspired architectures for cognitive or machine-learning applications.
- Memory Systems : optimizing DRAM/NVM chips, memory controllers, data placement, and security for big-data and datacenter workloads.
- Reliability : efficient mechanisms to support chipkill reliability in the memory system.
- Large cache design : methodologies to model large NUCA cache hierarchies, policies to organize data, and organizations in 3D.
- Interconnect design : leveraging different wires in a heterogeneous network for architectural innovation.
- Transactional memory : innovations for scalable hardware transactional memory.
Innovations in the Memory System , Rajeev Balasubramonian, Synthesis Lectures on Computer Architecture , Morgan and Claypool Publishers, 2019.
Multi-Core Cache Hierarchies , Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar, Synthesis Lectures on Computer Architecture , Morgan and Claypool Publishers, 2011.
( CACTI mirror site )
In Fall 2019, I am teaching a special topics class on Neuromorphic Architectures (CS 7960).
In Spring 2020, I am teaching CS 3810 Computer Organization.
I have also taught CS 7810 Advanced Computer Architecture,
CS 6810 Computer Architecture,
and the Architecture/VLSI Seminar (CS 7937).
Courses taught in the past are listed here.
- Naveen Muralimanohar , Ph.D. September 2008, Wire-Aware Cache Architectures , First employment: HP Labs, Current employment: Amazon.
- Niti Madan , Ph.D. January 2009, Leveraging Mixed-process 3D Die Stacking Technology for Cache Hierarchies and Reliability , First employment: Computing Innovation Fellow at IBM T.J. Watson, Current employment: AMD Research.
- Manu Awasthi , Ph.D. September 2011, Managing Data Locality in Future Memory Hierarchies Using a Hardware Software Co-Design Approach , First employment: Micron, Current employment: IIT Gandhinagar.
- Aniruddha Udipi , Ph.D. March 2012, Designing Efficient Memory for Future Computing Systems , First employment: ARM, Current employment: Google.
- Kshitij Sudan , Ph.D. October 2012, Data Placement for Efficient Main Memory Access , First employment: Samsung, Current employment: ARM.
- Niladrish Chatterjee , Ph.D. September 2013, Designing Efficient Memory Schedulers for Future Systems , First employment: NVidia.
- Seth Pugsley , Ph.D. May 2014, Opportunities for Near Data Computing in MapReduce Workloads , First employment: Intel.
- Manju Shevgoor , Ph.D. October 2015, Enabling Big Memory with Emerging Technologies, First employment: Intel.
- Ali Shafiee , Ph.D. August 2017, Hardware Accelerators for Deep Learning, First employment: Samsung.
- Vivek Venkatesan , M.S. December 2007, Criticality of On-Chip Wires , First employment: Sun (currently, Oracle).
- Byong Wu Chong, M.S. December 2012, Transactional Memory , First employment: Broadcom.
- Gita Sreekumar, M.S. December 2014, First employment: Qualtrics.
- Sahil Koladiya, M.S. May 2015, First employment: Cisco, Current employment: Amazon.
- Akhila Gundu, M.S. May 2015, First employment: Micron.
- Arjun Deb, M.S. May 2016, First employment: Xilinx.
- Chandru Nagarajan, M.S. May 2017, First employment: Micron.
- Meysam Taassori, Ph.D. student, DRAM Variation
- Karl Taht, Ph.D. student, Prefetching
- Anirban Nag, Ph.D. student, Machine Learning Accelerators
- Surya Narayanan, Ph.D. student, Neuromorphic Architectures
- Shirley Hon, M.S. student, Memory Compression
Life outside work
My blood pressure as an Assistant Professor was 30 points lower than what
it was as a grad student. Must have something to do with a
and a wonderful sport.