Rajeev Balasubramonian

Assistant Professor
School of Computing
University of Utah

CV | Detailed research page | Full publication list | Teaching page

Research

I'm co-organizing the 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI) at ISCA'08. Please submit good papers (deadline: Apr 18th).

Selected Representative Publications (Full list) :

• Architecting Efficient Interconnects for Large Caches with CACTI 6.0, Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi, selected to appear in IEEE Micro's Special issue on Top Picks from 2007 Computer Architecture Conferences , Jan/Feb 2008.
• Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, Technical Report UUCS-08-001, January 2008.
• Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
• Leveraging 3D Technology for Improved Reliability , Niti Madan, Rajeev Balasubramonian, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
• Power Efficient Approaches to Redundant Multithreading , Niti Madan, Rajeev Balasubramonian, IEEE Transactions on Parallel and Distributed Systems (Special Issue on CMP Architectures) , Vol. 18, No. 8, pp. 1066-1079, August 2007.
• Understanding the Impact of 3D Stacked Layouts on ILP , Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian, The Journal of Instruction-Level Parallelism (JILP) , Volume 9, June 2007.
• Interconnect Design Considerations for Large NUCA Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 34th International Symposium on Computer Architecture (ISCA-34) , San Diego, June 2007.
• Leveraging Wire Properties at the Microarchitecture Level , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, IEEE Micro , Vol. 26, No. 6, November/December 2006.
• Interconnect-Aware Coherence Protocols for Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 33rd International Symposium on Computer Architecture (ISCA-33) , Boston, June 2006.
• Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity , Naveen Muralimanohar, Karthik Ramani, and Rajeev Balasubramonian, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , Austin, March 2006.
• A Case for Increased Operating System Support in Chip Multi-Processors , David Nellans, Rajeev Balasubramonian, and Erik Brunvand, 2nd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, September 2005.
• Microarchitectural Wire Management for Performance and Power in Partitioned Architectures , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, and Venkatanand Venkatachalapathy, 11th International Symposium on High-Performance Computer Architecture (HPCA-11) , San Francisco, February 2005.
• Cluster Prefetch: Tolerating On-Chip Wire Delays in Clustered Microarchitectures , Rajeev Balasubramonian, 18th International Conference on Supercomputing (ICS-18) , Saint-Malo, June 2004.

• Interconnect design : leveraging different wires in a heterogeneous network for architectural innovation.
• Large cache design : methodologies to model large NUCA cache hierarchies, policies to organize data, reconfiguration within the hierarchy, on-chip network innovations, organizations in 3D.
• Transactional memory : innovations for scalable hardware transactional memory.
• Reliability : efficient verification of on-chip computation and communication.

Software Release

CACTI 6.0

Teaching

I am teaching CS 7820 Parallel Computer Architecture in Spring 2008. I teach CS 6810 Computer Architecture in the Fall semester.

I also organize the Architecture Reading Club every semester.

Courses taught in the past (including CS 3810 , CS 6810 , CS 7810 , CS 7820 ).

Students

• Naveen Muralimanohar , Ph.D. student, Interconnect-Aware Architectures
• Niti Madan , Ph.D. student, Efficient Mechanisms for Increased Reliability
• Manu Awasthi , Ph.D. student, Cache Hierarchies
• Vivek Venkatesan , M.S. student, Criticality of On-Chip Wires
• Seth Pugsley, Undergraduate student, Transactional Memory

Life outside work

My blood pressure as an Assistant Professor is 30 points lower than what it was as a grad student. Must have something to do with a wonderful wife and a wonderful sport. And now, the newest distraction.