Rajeev Balasubramonian

Associate Professor
School of Computing
University of Utah

ASPLOS 2014 | CV | Detailed research page | Full publication list | Teaching page | Utah Arch Research Group | Blog

Research

Recent Contributions (Full list of publications) :

• Blog
• Book: Multi-Core Cache Hierarchies
• JWAC Memory Scheduling Championship at ISCA 2012, based on the USIMM memory system simulation infrastructure.
• HPCA 2013: A Novel System Architecture for Web Scale Applications Using Lightweight CPUs and Virtualized I/O.
• MICRO 2012: Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.
• PACT 2012: Optimizing Datacenter Power with Memory System Levers for Guaranteed Quality-of-Service.
• ISCA 2012: LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems.
• HPCA 2012: Efficient Scrub Mechanisms for Error-Prone Emerging Memories.
• HPCA 2012: Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads.

Other Selected Publications (Full list of publications) :

• ISCA 2011: Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems.
• TOP PICKS 2011: CHOP: Integrating DRAM Caches for CMP Server Platforms.
• PACT 2010 Best Paper: Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers.
• ISCA 2010: Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores.
• ASPLOS 2010: Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement.
• HPCA 2010: Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks.
• HPCA 2010: CHOP: Adaptive Filter-based DRAM Caching for CMP Server Platforms.
• HPCA 2009: Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches.
• HPCA 2009: Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy.
• TOP PICKS 2008: Architecting Efficient Interconnects for Large Caches with CACTI 6.0.
• MICRO 2007: Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0.
• MICRO 2007: Leveraging 3D Technology for Improved Reliability.
• ISCA 2007: Interconnect Design Considerations for Large NUCA Caches.
• ISCA 2006: Interconnect-Aware Coherence Protocols for Chip Multiprocessors.
• HPCA 2005: Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.

• Memory Systems : optimizing memory controller and DRAM behavior for high performance and low energy.
• Large cache design : methodologies to model large NUCA cache hierarchies, policies to organize data, reconfiguration within the hierarchy, on-chip network innovations, organizations in 3D.
• Reliability : memory reliability and efficient verification of on-chip computation and communication.
• Interconnect design : leveraging different wires in a heterogeneous network for architectural innovation.
• Transactional memory : innovations for scalable hardware transactional memory.

Book

Multi-Core Cache Hierarchies , Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar, Synthesis Lectures in Computer Architecture , Morgan and Claypool Publishers, 2011.

Software Release

USIMM

CACTI 6.0 ( CACTI mirror site )

Teaching

I teach CS 7810 Advanced Computer Architecture in the Spring semester and CS 6810 Computer Architecture in the Fall semester.

I also organize the Architecture Reading Club every semester.

Courses taught in the past (including CS 3810 , CS 6810 , CS 7810 , CS 7820 ).

Students

Graduated:

• Naveen Muralimanohar , Ph.D. September 2008, Wire-Aware Cache Architectures , First employment: HP Labs.
• Niti Madan , Ph.D. January 2009, Leveraging Mixed-process 3D Die Stacking Technology for Cache Hierarchies and Reliability , First employment: Computing Innovation Fellow at IBM T.J. Watson, Current employment: Oracle.
• Manu Awasthi , Ph.D. September 2011, Managing Data Locality in Future Memory Hierarchies Using a Hardware Software Co-Design Approach , First employment: Micron.
• Aniruddha Udipi , Ph.D. March 2012, Designing Efficient Memory for Future Computing Systems , First employment: ARM.
• Kshitij Sudan , Ph.D. October 2012, Data Placement for Efficient Main Memory Access , First employment: Samsung.
• Vivek Venkatesan , M.S. December 2007, Criticality of On-Chip Wires , First employment: Sun (currently, Oracle).

Current:

• Niladrish Chatterjee , Ph.D. student, Memory Scheduling
• Seth Pugsley (brace yourself... this link has stunning graphics and Flash) , Ph.D. student, Processing Near Memory
• Manju Shevgoor , Ph.D. student, Memory Systems
• Ali Shafiee , Ph.D. student, Memory Systems
• Co-advising Dave Nellans , Ph.D. student, Optimizing OS Execution
• Byong Wu Chong, M.S. student, Transactional Memory

Life outside work

My blood pressure as an Assistant Professor was 30 points lower than what it was as a grad student. Must have something to do with a wonderful wife and a wonderful sport. And now, the newest distractions: Shurik and Anushka.