Rajeev Balasubramonian

Associate Professor
School of Computing
University of Utah

CV | Detailed research page | Full publication list | Teaching page | Utah Arch Research Group

Research

Selected Representative Publications (Full list) :

• Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement , Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis, 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV) , Pittsburgh, March 2010.
• Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , Bangalore, January 2010.
• Non-Uniform Power Access in Large Caches with Low-Swing Wires , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Conference on High Performance Computing (HiPC) , Kochi, December 2009 (Best paper award).
• OS Execution on Multi-Cores: Is Out-Sourcing Worthwhile? , David Nellans, Rajeev Balasubramonian, and Erik Brunvand, Position paper in ACM Operating System Review, Special Issue on Interaction among OS, Compilers, and Multicore Processors , April 2009.
• Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches , Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John Carter, 15th International Symposium on High-Performance Computer Architecture (HPCA-15) , Raleigh, February 2009.
• Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy , Niti Madan, Li Zhao (Intel), Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer (Intel), Srihari Makineni (Intel), Donald Newell (Intel), 15th International Symposium on High-Performance Computer Architecture (HPCA-15) , Raleigh, February 2009.
• Scalable and Reliable Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT-17) , Toronto, October 2008.
• Architecting Efficient Interconnects for Large Caches with CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), selected to appear in IEEE Micro's Special issue on Top Picks from 2007 Computer Architecture Conferences , Jan/Feb 2008.
• Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
• Leveraging 3D Technology for Improved Reliability , Niti Madan, Rajeev Balasubramonian, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
• Power Efficient Approaches to Redundant Multithreading , Niti Madan, Rajeev Balasubramonian, IEEE Transactions on Parallel and Distributed Systems (Special Issue on CMP Architectures) , Vol. 18, No. 8, pp. 1066-1079, August 2007.
• Understanding the Impact of 3D Stacked Layouts on ILP , Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian, The Journal of Instruction-Level Parallelism (JILP) , Volume 9, June 2007.
• Interconnect Design Considerations for Large NUCA Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 34th International Symposium on Computer Architecture (ISCA-34) , San Diego, June 2007.
• Leveraging Wire Properties at the Microarchitecture Level , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, IEEE Micro , Vol. 26, No. 6, November/December 2006.
• Interconnect-Aware Coherence Protocols for Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 33rd International Symposium on Computer Architecture (ISCA-33) , Boston, June 2006.
• Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity , Naveen Muralimanohar, Karthik Ramani, and Rajeev Balasubramonian, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , Austin, March 2006.
• Microarchitectural Wire Management for Performance and Power in Partitioned Architectures , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, and Venkatanand Venkatachalapathy, 11th International Symposium on High-Performance Computer Architecture (HPCA-11) , San Francisco, February 2005.

• Interconnect design : leveraging different wires in a heterogeneous network for architectural innovation.
• Large cache design : methodologies to model large NUCA cache hierarchies, policies to organize data, reconfiguration within the hierarchy, on-chip network innovations, organizations in 3D.
• Transactional memory : innovations for scalable hardware transactional memory.
• Reliability : efficient verification of on-chip computation and communication.

Software Release

CACTI 6.0

Teaching

I am teaching CS 7810 Advanced Computer Architecture this semester. I teach CS 6810 Computer Architecture in the Fall semester.

I also organize the Architecture Reading Club every semester.

Courses taught in the past (including CS 3810 , CS 6810 , CS 7810 , CS 7820 ).

Students

Graduated:

• Naveen Muralimanohar , Ph.D. September 2008, Wire-Aware Cache Architectures , First employment: HP Labs
• Niti Madan , Ph.D. January 2009, Leveraging Mixed-process 3D Die Stacking Technology for Cache Hierarchies and Reliability , First employment: Computing Innovation Fellow at IBM T.J. Watson
• Vivek Venkatesan , M.S. December 2007, Criticality of On-Chip Wires , First employment: Sun

Current:

• Manu Awasthi , Ph.D. student, Memory Controller Design
• Kshitij Sudan , Ph.D. student, Memory Hierarchies
• Aniruddha Udipi , Ph.D. student, Scalable Interconnects
• Seth Pugsley, Ph.D. student, Cache Coherence
• Niladrish Chatterjee , Ph.D. student, Customization for MPI Workloads
• Byong Wu Chong, M.S. student, Transactional Memory
• Co-advising Dave Nellans , Ph.D. student, Optimizing OS Execution

Life outside work

My blood pressure as an Assistant Professor is 30 points lower than what it was as a grad student. Must have something to do with a wonderful wife and a wonderful sport. And now, the newest distraction.