2013
Understanding
the Role of the Power Delivery Network in
3D-Stacked Memory Devices
Manjunath
Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev
Balasubramonian.
5th Workshop on
Energy-Efficient Design (held with ISCA-40), Tel Aviv, 2013. WEED 2013.
2012
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access
Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi Iyer.
45th Annual ACM/IEEE International Symposium on Microarchitecture. Vancouver, 2012. MICRO 2012.
Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads
Niladrish Chatterjee, Rajeev Balasubramonian, Naveen Muralimanohar, Al Davis, Norm Jouppi.
18th International Symposium on High Performance Computer Architecture. New Orleans, 2012. HPCA 2012.
USIMM: the Utah Simulated Memory Module. A Simulation Infrastructure for the JWAC Memory Scheduling Competition
Niladrish Chatterjee, Rajeev Balasubramonian, Manjunath Shevgoor, Seth H. Pugsley, Aniruddha N. Udipi, Ali Shaifei, Manu Awasthi, Kshitij Sudan, Zeshan Chishti.
School of Computing Technical Report. UUCS-12-002..
2010
Micro-pages: Increasing DRAM Efficiency with Locality-Aware Data Placement
Kshitij Sudan, Niladrish Chatterjee, Dave Nellans, Manu Awasthi, Rajeev Balsubramonian, Al Davis.
15th International Conference on Architectural Support for Programming Languages and Operating Systems.(ASPLOS 2010)
Rethinking DRAM Design and Organization for Energy-Constrained Multi-cores
Aniruddha Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norm Jouppi.
37th International Symposium on Computer Architecture. St. Malo, 2010. (ISCA 2010).
2009
Optimizing a Multi-Core Processor for Message Passing Workloads
Niladrish Chatterjee, Seth Pugsley, Josef Spjut, Rajeev Balasubramonian.
5th Workshop on Unique Chips and Systems. Boston, 2009. (UCAS-2009) (held in conjunction with ISPASS 2009).
