Architectural Level Wire Management

Wire delay is a major bottleneck in modern communication bound processors. VLSI techniques allow a variety of wire implementations with varying delay, power, and bandwidth characteristics. Careful management of these wires at microarchitectural level can improve both power and performance characteristics of a processor. An initial study of this approach on a clustered architecture showed a good potential (HPCA 05). Later, this technique was used to accelerate coherence transactions in a chip multiprocessor ( ISCA 06).