Hardware Transactional Memory (HTM)

Transactional Memory (TM) is viewed as a promising approach to simplify the task of parallel programming. Existing proposals on Hardware Transactional Memory (HTM) either have severe scalability issues or suffer from livelock problems. This work builds upon Stanford HTM model with lazy versioning and lazy conflict detection and proposes a scalable HTM implementation with novel commit algorithms that are free of deadlocks/livelocks. Compared to the current state-of-the-art implementation, the proposed algorithms show 7X reduction in commit delay and up to a 48X reduction in network messages on a 256 core CMP.

More details about this work can be found in this report.