"Wire Aware Cache Architectures" - Ph.D Thesis

Modern processors are severely constrained by wire delay. With the ever growing disparity between transistor and global wire delay, a careful analysis and a better understanding of interconnect models are necessary to alleviate the wire delay problem. VLSI techniques allow a number of wire implementations with varying delay, power, and bandwidth properties. My thesis advocates exposing wire properties to architects and demonstrates that prudent management of wires at microarchitectural level can lead to significant improvement in power and performance characteristics of future communication bound processors.

In addition to my Ph.D thesis, I have also worked on transactional memory, power and temperature aware design, and clustered architecture.

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