Novel Cache Pipelines for Large Caches

Future processors are capable of having a large level 2 or level 3 cache. While large caches help reduce cache miss rates, the wire delay problem associated with large structures severely limits the performance benefits of large caches. The project proposes novel pipelining techniques to address this problem and improve cache performance

The proposed optimizations are based on two key observations: 1) Address and data network have different requirements: the address network requires low-latency while the data network needs more bandwidth. 2) Even within an address message, some bits are more latency critical compared to others. Intelligent assigment of different bits to appropriate wire types can improve cache access time and reduce power.

More details about this work can be found in out ISCA 07 paper .