Publications

Conference and Journal Papers

Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores, Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, and Norm Jouppi, 37 International Symposium on Computer Architecture (ISCA-37), St. Malo, June 2010 (pdf)

Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks, Aniruddha N. Udipi, Naveen Muralimanohar, and Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16), Bangalore, January 2010 (pdf)

Non-Uniform Power Access in Large Caches with Low-Swing Wires, Aniruddha N. Udipi, Naveen Muralimanohar, and Rajeev Balasubramonian, 16th International Conference on High-Performance Computing (HiPC-16), Kochi, December 2009 (Best Paper Award) (pdf)

Leveraging 3D PCRAM Technologies to Reduce Checkpoint Overhead in Future Exascale Systems, Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, and Yuan Xie, 22nd Conference on Supercomputing (SC-22), Oregon, November 2009 (pdf)

Optimizing Communication and Locality in a 3D Stacked Reconfigurable Cache Hierarchy, Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishanker Iyer, Srihari Makineni, and Donald Newell, 15th International Conference on High-Performance Computer Architecture (HPCA-15), North Carolina, February 2009 (pdf)

Scalable and Reliable Communication for Hardware Transactional Memory, Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, and Rajeev Balasubramonian, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT-17), Toronto, October 2008 (pdf)

Architecting Efficient Interconnects for Large Caches with CACTI 6.0, Naveen Muralimanohar, Rajeev Balasubramonian, and Norm Jouppi, selected to appear in IEEE Micro's Special issue on Top Picks, Jan/Feb 2008 (pdf)

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0, Naveen Muralimanohar, Rajeev Balasubramonian, and Norm Jouppi, 40th International Symposium on Microarchitecture (MICRO-40), Chicago, December 2007 (pdf) (slides)

Interconnect Design Considerations for Large NUCA Caches, Naveen Muralimanohar and Rajeev Balasubramonian, 34th International Symposium on Computer Architecture (ISCA-34), San Diego, June 2007 (pdf) (slides)

The Effect of Interconnect Design on the Performance of Large L2 Caches, Naveen Muralimanohar and Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2), Yorktown Heights, October 2006 (pdf) (slides)

Leveraging Wire Properties at the Microarchitectural Level, Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, IEEE Micro, Vol. 26, No. 6, Nov/Dec 2006 (pdf)

Interconnect-Aware Coherence Protocols for Chip Multiprocessors, Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, International Symposium on Computer Architecture (ISCA-33), Boston, June 2006 (pdf) (slides)

Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, March 2006 (pdf) (slides)

Microarchitectural Wire Management for Performance and Power in Partitioned Architectures, Rajeev Balasubramonian, Naveen Muralimanohar, Karthikr Ramani, and Venkatanand Venkatachalapathy, 11th International Symposium on High-Performance Computer Architecture (HPCA-11), San Francisco, February 2005 (pdf) (slides)

Workshop Papers

A Case Study of Incremental and Background Hybrid In-Memory Checkpointing, Xiangyu Dong, Naveen Muralimanohar, Norman Jouppi, and Yuan Xie, Workshop on Exascale Evaluation and Research Techniques, held in conjunction with ASPLOS-15, Pittsburgh, March 2010 (pdf)

Wire Management for Coherence Traffic in Chip Multiprocessors, Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 6th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-32, Madison, June 2005 (pdf)

Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors, Karthik Ramani, Naveen Muralimanohar, and Rajeev Balasubramonian, 5th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-31, Munich, June 2004 (pdf) (slides)

Design downloaded from Free Templates - your source for free web templates