- Research Interests:
- Automatic performance tuning, Model-guided empirical optimization,
Interprocedural analysis and optimization,
parallelizing compilers, programming support for optimization
and parallelization, PIM-based architectures, compiling to FPGA-based systems
- School of Computing MEB 3466
- University of Utah
- Salt Lake City, UT 84112
- (801) 585-1039
- E-mail: firstname.lastname@example.org
Our research focuses on compiler-based approaches to obtaining high performance on state-of-the-art and experimental architectures, including multi-cores, GPUs and petascale platforms. We are developing auto-tuning compiler technology to systematically map application code to make efficient use of these diverse architectures. An auto-tuning compiler generates a set of alternative implementations of a computation, and uses empirical measurement to select the best-performing solution. Our compiler can work automatically or collaboratively with application programmers to accelerate their performance tuning and in some cases, produce results far better than is possible with manual tuning. Our group has access to DOE Leadership Class computing facilities, the University of Utah Center for High Performance Computing systems, and an Nvidia Tesla system with over 30,000 cores.
Current Professional Activities
ACM History Committee, Chair
Program Chair, CGO 2009
Workshop Co-Chair, SC 08
Crash Course in Compilers for Parallel Computing, Fall 2008
CS 6963, Parallel Programming for GPUs, Spring 2009
CS 4961, Parallel Programming, Fall 2009
CS 6963, Parallel Programming for GPUs, Spring 2010
CS 4961, Parallel Programming, Fall 2010
CS 6963, Parallel Programming for GPUs, Spring 2011
CS 4961, Parallel Programming, Fall 2011
CS 6235, Parallel Programming for Many-Core Architectures, Spring 2012
CS 4230, Parallel Programming, Fall 2012
CS 6235, Parallel Programming for Many-Core Architectures, Spring 2013
- DIVA, a Data-Intensive Architecture
- DEFACTO, Design Environment for Adaptive Computing Technology
Autotuning and Specialization: Speeding up Nek5000 with Compiler Technology, Jaewook Shin, Mary W. Hall, Jacqueline Chame, Chun Chen, Paul Fischer, Paul D. Hovland, International Conference on Supercomputing, June, 2010.
Loop Transformation Recipes for Code Generation and Auto-Tuning ,
Mary Hall, Jacqueline Chame, Chun Chen, Jaewook Shin, Gabe Rudy, Malik Murtaza Khan,
International Workshop on Languages and Compilers for Parallel Computing,
Autotuning and specialization: Speeding up matrix multiply for small matrices with compiler technology ,
Jaewook Shin, Mary W. Hall, Jacqueline Chame, Chun Chen,
Paul D. Hovland,
Fourth International Workshop on Automatic Performance Tuning, October, 2009.
A scalable auto-tuning framework for compiler optimization,
Jeffrey K. Hollingsworth,
International Parallel and Distributed Processing Symposium, May, 2009.
Compiler Research: The Next Fifty Years,
Communications of the ACM, Vol. 52:2, February, 2009.