Research
Research Interests
I am primarily interested in memory hierarchy design for Chip Multi Processors (CMPs), at all levels of the hierarchy. More specifically, I am interested in techniques to efficiently manage data and capacity in large, last-level caches and multi-socket, single-board NUMA main memories. Recently, I have been exploring mechanisms to mitigate the problem of resistance drift in phase-change memory (PCM) multi-level cells (MLCs).In the past, I have also looked at leveraging 3D stacking to reduce delays in critical pipeline loops in clustered micro-architectures, and algorithms to reduce on-chip traffic in hardware transactional memory implementations.