Publications
Journals
- Understanding the Impact of 3D Stacked Layouts on ILP, Journal of Instruction Level Parallelism (JILP), Volume 7, 2007 (Bibtex)
- Managing Data Placement in Systems with Multiple Memory Controllers, International Journal of Parallel Programming (IJPP), to appear, 2011 (Bibtex)
Refereed Conferences/Workshops
- Efficient Scrub Mechanisms for Error-Prone Emerging Memories, 18th International Symposium on High Performance Computer Architecture (HPCA), New Orleans, February 2012 (Bibtex)
- Prediction Based DRAM Row-Buffer Management in the Many-Core Era, 20th International Conference on Parallel Architecture and Compilation Techniques (PACT), Poster Track, Galveston Island, October 2011 (Bibtex)
- Handling PCM Resistance Drift with Device, Circuit, Architecture, and System Solutions, 2nd Non-Volatile Memories Workshop (NVMW), San Diego, March 2011 [Slides](Bibtex)
- Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers, 19th International Conference on Parallel Architecture and Compilation Techniques (PACT) (Best Paper Award) , Vienna, September 2010 [Slides](Bibtex)
- Increasing DRAM Efficiency with Locality-Aware Data Placement , 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Pittsburgh, March 2010 (Bibtex)
- Dynamic Page Placement to Manage Capacity, Replication, and Sharing within Large Caches, 15th International Conference on High Performance Computer Architecture (HPCA), Raleigh, February 2009 [Slides](Bibtex)
- Scalable and Reliable Communication for Hardware Transactional Memory, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), Toronto, October 2008. (Bibtex)
- Exploring the Design Space for 3D Clustered Architectures, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2), Yorktown Heights, October 2006. [Slides](Bibtex)
Other
- Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory, School of Computing Technical Report UUCS-08-001, January 2008
Posters
- ABP : Predictor Based Management of DRAM Row Buffers, School of Computing Grad Research Day, Spring 2010
- Controlling Page Placement to Manage Large Caches (Best Poster Runner-up), School of Computing Grad Research Day, Spring 2009
- Scalable and Reliable Communication for Hardware Transactional Memory, School of Computing Grad Research Day, Spring 2008
- Understanding the Impact of 3D Stacked layouts on ILP, School of Computing Grad Research Day, Spring 2007
- How NOT to have a Nuclear Reactor for a Microprocessor, School of Computing Grad Research Day, Spring 2006