HPCA-19 Conference Program

Schedule Overview:

Saturday , February 23th:

El Chino VIP 1
Madrid 1
Ghent U.
Madrid 2
Madrid 2

Sunday , February 24th:

El Chino VIP 1
El Chino VIP 1
U. Pittsburgh
Madrid 1
Madrid 2
Intel Labs
El Chino VIP 2

Huawei Sponsored Welcome Reception: 6pm - 8pm

Monday, February 25th:

8:00am-8:30am Opening Remarks  
8:30am-9:50am Keynote I: Kevin Nowka, Director, IBM Research - Austin Espana
9:50am-10:20am Break  
10:20am-12:00pm Session 1: Power and Energy I (Rakesh Kumar) Espana I
12:00pm-1:30pm Lunch  
1:30pm-2:45pm Session 2A: Microarchitecture (Karu Sankaralingam) Espana I
Session 2B: Scheduling and Virtual Machines (Michael Taylor) Madrid 2&3
2:45pm-3:00pm Break  
3:00pm-4:40pm Session 3A: Caches (Thomas Wenisch) Espana I
Session 3B: Industrial Track (Brad Beckmann) Madrid 2&3
4:40pm-4:55pm Break  
4:55pm-6:10pm Session 4A: Non-volatile Memory (Gabriel Loh) Espana I
Session 4B: Secure and Reliable Architectures (XiaoYao Liang) Madrid 2&3
6:45pm-7:45pm TCCA Business Meeting Madrid 2

Tuesday, February 26th:

8:30am-9:50am Keynote II: Katherine Yelick, Professor, UC Berkeley Espana
9:50am-10:20am Break  
10:20am-12:00pm Session 5: Best Paper Nominees (Dean Tullsen) Espana I
12:00pm-1:30pm Lunch  
1:30pm-2:45pm Session 6A: GPUs I (Mattan Erez) Espana I
Session 6B: Interconnection Networks I (YinHe Han) Madrid 2&3
2:45pm-3:00pm Break  
3:00pm-4:15pm Session 7A: Power and Energy II (Jason Mars) Espana I
Session 7B: Best of Computer Architecture Letters (Lieven Eeckhout ) Madrid 2&3
4:30pm-10:00pm Excursion/Banquet: Splendid China & China Folk Culture Villages  

Wednesday, February 27th:

8:00am-9:40am Session 8A: Heterogeneous and Adaptive Architectures (LingJia Tang) Espana I
Session 8B: Interconnection Networks II (Chris Wilkerson) Madrid 2&3
9:40am-10:00am Break  
10:00am-10:50am Session 9A: Near-threshold Computing (Benjamin Lee) Espana I
Session 9B: Coherence and Consistency (JunLi Gu) Madrid 2&3
10:50am-12:05pm Session 10A: DRAM/Memory (Ramon Canal) Espana I
Session 10B: GPUS II (Satish Narayansamy) Madrid 2&3



Monday, February 25th:

8:00am-8:30am Opening Remarks

8:30am-9:50am Keynote I (Espana)

Finding Meaning in Big Data

Kevin Nowka, Director, IBM Research - Austin

9:50am-10:20am Break

10:20am-12:00pm Session 1: Power and Energy I (Espana I)

Session Chair: Rakesh Kumar

Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures

Emily Blem, Jaikrishnan Menon, and Karthikeyan Sankaralingam (University of Wisconsin)

High-performance and Energy-efficient Mobile Web Browsing on Big/Litttle Systems

Yuhao Zhu and Vijay Janapa Reddi (University of Texas)

Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power

Yebin Lee, Soontae Kim, Seokin Hong, and Jongmin Lee (KAIST)

Enabling Distributed Generation Powered Sustainable High-Performance Data Center

Chao Li, Ruijin Zhou, and Tao Li (University of Florida)

12:00pm-1:30pm Lunch

1:30pm-2:45pm Session 2

Session 2A: Microarchitecture (Espana I)

Session Chair: Karu Sankaralingam

A Group-Commit Mechanism for ROB-Based Processors Implementing the x86 ISA

Furat Afram, Hui Zeng, and Kanad Ghose (SUNY at Binghamton)

Store-Load-Branch (SLB) Predictor: A Compiler Assisted Branch Prediction for Data Dependent Branches

M. Umar Farooq, Khubaib, and Lizy K. John (University of Texas)

Two Level Bulk Preload Branch Prediction

James Bonanno, Adam Collura, Daniel Lipetz, Ulrich Mayer, Brian Prasky, and Anthony Saporito (IBM)

Session 2B: Scheduling and Virtual Machines (Madrid 2&3)

Session Chair: Michael Taylor

ReCaP: A Region-Based Cure for the Common Cold (Cache)

Jason Zebchuk, Harold W. Cain, Xin Tong, Vijayalakshmi Srinivasan, and Andreas Moshovos (University of Toronto, IBM)

Navigating Heterogeneous Processors with Market Mechanisms

Marisabel Guevara, Benjamin Lubin, and Benjamin C. Lee (Duke University, Boston University)

Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems

Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, and Mani Azimi (University of Michigan, Carnegie Mellon University, Intel)

2:45pm-3:00pm Break

3:00pm-4:40pm Session 3

Session 3A: Caches (Espana I)

Session Chair: Thomas Wenisch

Improving Multi-Core Performance Using Mixed-Cell Cache Architecture

Samira Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, and Daniel A. Jimenez (Intel, Carnegie Mellon University, and Texas A&M University)

ECM : Effective Capacity Maximizer for High-Performance Compressed Caching

Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Junghee Lee, and Jongman Kim (Georgia Institute of Technology, Daegu University, University of Cyprus)

Architecting Embedded DRAM for Energy-Efficient Large Last-Level Caches

Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, and Bruce Jacob (University of Maryland, Intel)

Modeling Performance Variation Due to Cache Sharing

Andreas Sandberg, Andreas Sembrant, Erik Hagersten, and David Black-Schaffer (Uppsala University)

Session 3B: Industrial Track (Madrid 2&3)

Session Chair: Brad Beckmann

A Novel System Architecture for Web Scale Applications Using Lightweight CPUs and Virtualized I/O

Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, and Rajeev Balasubramonian (University of Utah, SeaMicro, AMD)

Cost Effective Data Center Servers

Rui Hou, Tao Jiang, Liuhang Zhang, Pengfei Qi, Jianbo Dong, Haibin Wang, Xiongli Gu, and Shujie Zhang (Chinese Academy of Sciences, Huawei)

Optimizing Google’s Warehouse Scale Computers: The NUMA Experience

Lingjia Tang, Jason Mars, Xiao Zhang, Robert Hagmann, Robert Hundt, and Eric Tune (UCSD, Google)

Runnemede: An Architecture for Ubiquitous High-Performance Computing

Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua Fryman, Ivan Ganev, Roger A. Golliver, Rob Knauerhase, Richard Lethin, Benoit Meister, Asit K. Mishra, Wilfred Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, and Jianping Xu (Intel, UIUC, Reservoir Labs)

4:40pm-4:55pm Break

4:55pm-6:10pm Session 4

Session 4A: Non-volatile Memory (Espana I)

Session Chair: Gabriel Loh

Exploring High-Performance and Energy Proportional Interface for Phase Change Memory Systems

Zhongqi Li, Ruijin Zhou and Tao Li (University of Florida)

Coset Coding to Extend the Lifetime of Memory

Adam N. Jacobvitz, A. Robert Calderbank, and Daniel J. Sorin (Duke University)

i2WAP: Improving Non-Volatile Cache Lifetime by Reducing Inter- and Intra-Set Write Variations

Jue Wang, Xiangyu Dong, Norman P. Jouppi, and Yuan Xie (Pennsylvania State University, Qualcomm, AMD, Hewlett-Packard)

Session 4B: Secure and Reliable Architectures (Madrid 2&3)

Session Chair: XiaoYao Liang

Architecture Support for Guest-Transparent VM Protection from Untrusted Hypervisor and Physical Attacks

Yubin Xia, Yutao Liu, and Haibo Chen (Shanghai Jiao Tong University)

SCRAP: Architecture for Signature-Based Protection from Code Reuse Attacks

Mehmet Kayaalp, Timothy Schmitt, Junaid Nomani, Dmitry Ponomarev, and Nael Abu-Ghazaleh (Binghamton University)

Adaptive Reliability Chipkill Correct (ARCC)

Xun Jian and Rakesh Kumar (UIUC)

6:45pm-7:45pm: TCCA  Business Meeting (Madrid 2)

Tuesday, February 26th:

8:30am-9:50am Keynote II (Espana)

Antisocial Parallelism: Avoiding, Hiding and Managing Communication

Katherine Yelick, Professor, UC Berkeley

9:50am-10:20am Break

10:20am-12:00pm Session 5: Best Paper Nominees (Espana I)

Session Chair: Dean Tullsen

Accelerating Write by Exploiting PCM Asymmetries

Jianhui Yue and Yifeng Zhu (University of Maine)

Hybrid Latency Tolerance for Robust Energy-Efficiency on 1000-Core Data Parallel Processors

Neal C. Crago, Omid Azizi, Steven S. Lumetta, and Sanjay J. Patel (Intel, HiCAMP Systems, UIUC)

Optimizing Virtual Machine Scheduling in NUMA Multicore Systems

Jia Rao, Kun Wang, Xiaobo Zhou, and Cheng-Zhong Xu (University of Colorado at Colorado Springs, Wayne State University)

Sonic Millip3De: Massively Parallel 3D-Stacked Accelerator for 3D Ultrasound (Best Paper Award)

Richard Sampson, Ming Yang, Siyuan Wei, and Chaitali Chakrabarti, and Thomas F. Wenisch (University of Michigan, Arizona State University)

12:00pm-1:30pm Lunch

1:30pm-2:45pm Session 6

Session 6A: GPUs I (Espana I)

Session Chair: Mattan Erez

Power-efficient Computing for Compute-intensive GPGPU Applications

Zohaib Gilani, Nam Sung Kim, and Michael Schulte (University of Wisconsin, AMD)

Power-performance Co-optimization of Throughput Core Architecture using Resistive Memory

Nilanjan Goswami, Bingyi Cao, and Tao Li (University of Florida)

Reducing GPU Offload Latency Via Fine-Grained CPU-GPU Synchronization

Lustig and Margaret Martonosi (Princeton University)

Session 6B: Interconnection Networks I (Madrid 2&3)

Session Chair: YinHe Han

Worm-Bubble Flow Control

Lizhong Chen and Timothy M. Pinkston (USC)

Breaking the On-Chip Latency Barrier Using SMART

Tushar Krishna, Chia-Hsin Owen Chen, Woo Cheol Kwon, and Li-Shiuan Peh (MIT)

TS-Router: On Maximizing the Quality-of-Allocation in the On-Chip Network

Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, and Chung-Ta King (National Tsing Hua University, Pennsylvania State University, AMD)

2:45pm-3:00pm Break

3:00pm-4:15pm Session 7

Session 7A: Power and Energy II (Espana I)

Session Chair: Jason Mars

Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies

Aditya Agrawal, Prabhat Jain, Amin Ansari, and Josep Torrellas (UIUC)

Warped Register File: A Power Efficient Register File for GPGPUs

Mohammad Abdel-Majeed and Murali Annavaram (USC)

Disintegrated Control for Energy-Efficient and Heterogeneous Memory Systems

Tae Jun Ham, Bharath K. Chelepalli, Neng Xue, and Benjamin C. Lee (Duke University)

Session 7B: Best of Computer Architecture Letters (Madrid 2&3)

Session Chair: Lieven Eeckhout

4:30pm-10:00pm: Excursion/Banquet

Splendid China & China Folk Culture Villages


Wednesday, February 27th:

8:00am-9:40am Session 8

Session 8A: Heterogeneous and Adaptive Architectures (Espana I)

Session Chair: LingJia Tang

Illusionist: Transforming Lightweight Cores into Aggressive Cores on Demand

Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, and Scott Mahlke (UIUC, Northrop Grumman, Intel, University of Michigan)

ESESC: A Fast Multicore Simulator Using Time-Based Sampling

Ehsan K. Ardestani and Jose Renau (UC Santa Cruz)

How to Implement Effective Prediction and Forwarding for Fusable Dynamic Multicore Architectures

Behnam Robatmili, Dong Li, Hadi Esmaeilzadeh, Madhu Saravana Sibi Govindan, Aaron Smith, Andrew Putnam, Doug Burger, and Steve Keckler (Qualcomm, University of Texas, University of Washington, AMD, Microsoft Research, NVIDIA)

Bridging the Semantic Gap: Emulating Biological Neuronal Behaviors with Simple Digital Neurons

Andrew Nere, Atif Hashmi, Mikko Lipasti, and Giulio Tononi (University of Wisconsin)

Session 8B: Interconnection Networks II (Madrid 2&3)

Session Chair: Chris Wilkerson

Layout-conscious Random Topologies for HPC Off-chip Interconnects

Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, and Henri Casanova (National Institute of Informatics, Keio University, University of Hawaii at Manoa)

Scaling Towards Kilo-Core Processors with Asymmetric High Radix Topologies

Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David Blaauw, and Trevor Mudge (University of Michigan)

Energy-Efficient Interconnect via Router Parking

Ahmad Samih, Anil Krishna, Yan Solihin, Ren Wang, and Christian Maciocco (Intel, Qualcomm, NCSU)

In-Network Traffic Regulation for Transactional Memory

Lihang Zhao, Woojin Choi, Lizhong Chen, and Jeff Draper (USC)

9:40am-10:00am Break

10:00am-10:50am Session 9

Session 9A: Near-threshold Computing (Espana I)

Session Chair: Benjamin Lee

Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling

Tayyeb Mahmood, Soontae Kim, and Seokin Hong (KAIST)

Toward Energy-Efficient Manycores for Near-Threshold Computing

Ulya R. Karpuzcu, Abhishek Sinkar, Nam Sung Kim, and Josep Torrellas (UIUC, University of Wisconsin)

Session 9B: Coherence and Consistency (Madrid 2&3)

Session Chair: JunLi Gu

Rainbow: Efficient Memory Dependence Recording with High Replay Parallelism for Relaxed Memory Model

Xuehai Qian, He Huang, Benjamin Sahelices, and Depei Qian (UIUC, AMD, University of Valladolid, Beihang University)

High-Speed Formal Verification of Heterogeneous Coherence Hierarchies

Jesse G Beu, Jason A Poovey, Eric R Hein, and Thomas M Conte (Georgia Institute of Technology)

10:50am-12:05pm Session 10

Session 10A: DRAM/Memory (Espana I)

Session Chair: Ramon Canal

Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture

Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu (CMU)

A Case for Refresh Pausing in DRAM Memory Systems

Prashant Nair, Chia-Chen Chou, and Moinuddin Qureshi (Georgia Tech)

MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems

Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, and Onur Mutlu (CMU)

Session 10B: GPUS II (Madrid 2&3)

Session Chair: Satish Narayansamy

Cache Coherence for GPU Architectures

Inderpreet Singh, Arrvindh Shriraman, Wilson W. L. Fung, Mike O'Connor, and Tor M. Aamodt (University of British Columbia, Simon Fraser University, AMD, Stanford)

The Dual-Path Execution Model for Efficient GPU Control Flow

Minsoo Rhu and Mattan Erez (The University of Texas)

A Multiple SIMD, Multiple Data (MSMD) Architecture: Parallel Execution of Dynamic and Static SIMD Fragments

Yaohua Wang, Shuming Chen, Jianghua Wan, Jiayuan Meng, Kai Zhang, Wei Liu, and Xi Ning (National University of Defense Technology, University of Virginia)