LIQUN (LEGION) CHENG

School of Computing, University of Utah     

legion@cs.utah.edu

Areas of Interest:

Computer Architecture, Performance Analysis, Parallel and Distributed Computing

Education: 

PhD

March 2007     

Computer Science, University of Utah
Advisor: Professor John Carter

BS

2002

Computer Sience, Shanghai Jiao Tong University (98TR)

      

Work Experience:

Summer Intern             

2006

Intel Corporation, DEG Architecture and Planning

I extended the existing simulator to support multi-level cache hierarchy, evaluated different cache coherence protocols, and invented two novel caching techniques.

Research Assistant      

2004-2007    

University of Utah & SGI        

In collaboration with SGI, I designed and evaluated ideas for improving memory performance of next generation large-scale shared memory multiprocessors.

Summer Intern             

2005

Intel Corporation, DEG Architecture and Planning

I implemented snoop filter component for the chipset simulator, and invented three novel replacement policies.

Research Assistant       

2003

University of Utah & SGI, DARPA HPCS

Ultraviolet project designed a peta-scale system, targeted for the 2010 timeframe. I developed several components for the simulator.

Research Assistant       

2001

Shanghai Jiao Tong University, CIT Lab                        

I was the key designer for a shared virtual environment based on Java and VRML

 

Publications:

Extending CC-NUMA Systems to Support Write Update Optimizations

Liqun Cheng and John B. Carter, Supercomputing 2008 (SC08)

 

Write Update Optimizations for CC-NUMA Systems

Liqun Cheng and John B. Carter, The Eleventh Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-11), held in conjunction with HPCA-14, 2008

 

An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing

Liqun Cheng, John B. Carter and Donglai Dai, International Symposium on High-Performance Computer Architecture, HPCA-13, 2007

 

Interconnect-Aware Coherence Protocols for Chip Multiprocessors

Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter International Symposium on Computer Architecture, ISCA -33 2006

 

Leveraging Wire Properties at the Microarchitecture Level

Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, IEEE Micro, 2006.

 

Reducing Back-Invalidation in Snoop Filter for Database Workloads              

Liqun Cheng, Lily P Looi, Kai Cheng and Faye Briggs Technical report 133340, Intel Corporation, August 2005

 

Wire Management for Coherence Traffic in Chip Multiprocessors  

Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 6th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-32.

 

Fast Barriers for Scalable ccNUMA Systems

Liqun Cheng and John B. Carter, International Conference on Parallel Processing, ICPP 2005

 

Fast Synchronization on Shared-Memory Multiprocessors: An Architectural Approach
Zhen Fang, Lixin Zhang, Liqun Cheng, John Carter and Mike Parker,  Journal of Parallel and Distributed Computing, JPDC 2005

 

An O(1) Time Complexity Software Barrier

Liqun Cheng and John B. Carter, Technical report UUCS-04-018, Department of Computer Science, University of Utah

 

Patents:

Using Critical Information to Route Cache Coherency Communications

Filed with Intel Corporation, August 2008, US patent pending

 

Apparatus and Method of Controlling Cache Sharing on Shared Memory Computer System

Filed with Silicon Graphics Inc. May 2006, US patent 20060265554

 

Microarchitectural Wire Management for Performance and Power in Partitioned Architectures

Filed with Univ. of Utah, Nov 2005, US patent 20070192541

 

Exclusive Ownership Snoop Filter

Filed with Intel Corporation. August 2005, US patent 20080005485

 

Way Hint Line Replacement Technique for a Snoop Filter

Filed with Intel Corporation. August 2005, US patent 20070233965

 

Preselecting E/M Line Replacement Technique for a Snoop Filter

Filed with Intel Corporation. August 2005, US patent 20070239941

 

Awards:

Third Prize in National Mathematics Modeling Competition, 2000

Shanghai Jiao Tong University Outstanding Students, 1999

Second Prize in National Physics Competition for Senior High Students, 1998

Second Prize in National Mathematics Competition for Senior High Students, 1998

First Prize in National Physics Competition for Junior High Students, 1995

Third Prize in National Mathematics Competition for Junior High Students, 1995

 

Professional Activities:

Reviewer for:  PACT04, WMPI04, HPCA05, ICPP06, SC08

Web Chair for: WMPI06, HPCA08

IEEE Member, ACM Member

 

References:

Available upon request