Index: apps/dirtest/rsim_params =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/apps/dirtest/rsim_params,v retrieving revision 1.3 retrieving revision 1.4 diff --context -r1.3 -r1.4 *** apps/dirtest/rsim_params 2002/09/25 22:20:38 1.3 --- apps/dirtest/rsim_params 2002/11/25 17:13:31 1.4 *************** *** 98,115 **** MMC_latency 16 MMC_frequency 2 - MMC_isfortran 0 - MMC_prefetch_on 0 - MMC_testlimit 0 - MMC_prefetch_queue 0 - MMC_replacement FIFO - MMC_perfect_cache 0 - MMC_writeupdate 0 - MMC_cache_size 0 - MMC_cache_assoc 4 - MMC_saddr_check 0 - MMC_buffer_size 8 - MMC_buffer_assoc 4 DRAM_latency 18 DRAM_frequency 2 --- 98,103 ---- Index: apps/exec/rsim_params =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/apps/exec/rsim_params,v retrieving revision 1.4 retrieving revision 1.5 diff --context -r1.4 -r1.5 *** apps/exec/rsim_params 2002/08/28 18:30:34 1.4 --- apps/exec/rsim_params 2002/11/25 17:13:31 1.5 *************** *** 97,114 **** MMC_latency 16 MMC_frequency 2 ! MMC_isfortran 0 ! MMC_prefetch_on 0 ! MMC_testlimit 0 ! MMC_prefetch_queue 0 ! MMC_replacement FIFO ! MMC_perfect_cache 0 ! MMC_writeupdate 0 ! MMC_cache_size 0 ! MMC_cache_assoc 4 ! MMC_saddr_check 0 ! MMC_buffer_size 8 ! MMC_buffer_assoc 4 DRAM_latency 18 DRAM_frequency 2 --- 97,103 ---- MMC_latency 16 MMC_frequency 2 ! MMC_sim detailed DRAM_latency 18 DRAM_frequency 2 Index: apps/filetest/rsim_params =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/apps/filetest/rsim_params,v retrieving revision 1.5 retrieving revision 1.6 diff --context -r1.5 -r1.6 *** apps/filetest/rsim_params 2002/09/25 22:20:38 1.5 --- apps/filetest/rsim_params 2002/11/25 17:13:32 1.6 *************** *** 98,109 **** L2C_mshr 4 MMC_frequency 4 ! MMC_testlimit 0 ! MMC_writeupdate 0 ! MMC_saddr_check 1 ! MMC_buffer_size 8 ! MMC_buffer_assoc 4 ! MMC_sim_on 1 MMC_latency 26 DRAM_latency 18 --- 98,104 ---- L2C_mshr 4 MMC_frequency 4 ! MMC_sim detailed MMC_latency 26 DRAM_latency 18 Index: apps/longf/rsim_params =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/apps/longf/rsim_params,v retrieving revision 1.3 retrieving revision 1.4 diff --context -r1.3 -r1.4 *** apps/longf/rsim_params 2002/08/28 18:30:39 1.3 --- apps/longf/rsim_params 2002/11/25 17:13:32 1.4 *************** *** 99,105 **** MMC_latency 16 MMC_frequency 2 ! DRAM_latency 18 DRAM_frequency 2 DRAM_scheduler_on 0 --- 99,106 ---- MMC_latency 16 MMC_frequency 2 ! MMC_sim detailed ! DRAM_latency 18 DRAM_frequency 2 DRAM_scheduler_on 0 Index: apps/signals/rsim_params =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/apps/signals/rsim_params,v retrieving revision 1.3 retrieving revision 1.4 diff --context -r1.3 -r1.4 *** apps/signals/rsim_params 2002/08/28 18:30:48 1.3 --- apps/signals/rsim_params 2002/11/25 17:13:33 1.4 *************** *** 97,114 **** MMC_latency 16 MMC_frequency 2 ! MMC_isfortran 0 ! MMC_prefetch_on 0 ! MMC_testlimit 0 ! MMC_prefetch_queue 0 ! MMC_replacement FIFO ! MMC_perfect_cache 0 ! MMC_writeupdate 0 ! MMC_cache_size 0 ! MMC_cache_assoc 4 ! MMC_saddr_check 0 ! MMC_buffer_size 8 ! MMC_buffer_assoc 4 DRAM_latency 18 DRAM_frequency 2 --- 97,103 ---- MMC_latency 16 MMC_frequency 2 ! MMC_sim detailed DRAM_latency 18 DRAM_frequency 2 Index: apps/socket_test/rsim_params =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/apps/socket_test/rsim_params,v retrieving revision 1.2 retrieving revision 1.3 diff --context -r1.2 -r1.3 *** apps/socket_test/rsim_params 2002/08/28 18:30:49 1.2 --- apps/socket_test/rsim_params 2002/11/25 17:13:33 1.3 *************** *** 101,118 **** MMC_latency 16 MMC_frequency 2 ! MMC_isfortran 0 ! MMC_prefetch_on 0 ! MMC_testlimit 0 ! MMC_prefetch_queue 0 ! MMC_replacement FIFO ! MMC_perfect_cache 0 ! MMC_writeupdate 0 ! MMC_cache_size 0 ! MMC_cache_assoc 4 ! MMC_saddr_check 0 ! MMC_buffer_size 8 ! MMC_buffer_assoc 4 DRAM_latency 18 DRAM_frequency 2 --- 101,107 ---- MMC_latency 16 MMC_frequency 2 ! MMC_sim detailed DRAM_latency 18 DRAM_frequency 2 Index: apps/sysconf/rsim_params =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/apps/sysconf/rsim_params,v retrieving revision 1.2 retrieving revision 1.3 diff --context -r1.2 -r1.3 *** apps/sysconf/rsim_params 2002/08/28 18:30:49 1.2 --- apps/sysconf/rsim_params 2002/11/25 17:13:34 1.3 *************** *** 98,103 **** --- 98,104 ---- MMC_latency 16 MMC_frequency 2 + MMC_sim 1 DRAM_latency 18 DRAM_frequency 2 Index: bin/rsim_params =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/bin/rsim_params,v retrieving revision 1.2 retrieving revision 1.3 diff --context -r1.2 -r1.3 *** bin/rsim_params 2002/07/15 23:07:10 1.2 --- bin/rsim_params 2002/11/25 17:13:34 1.3 *************** *** 105,111 **** ! ##### Uncache Buffer Parameters ##### ubuftype comb # combining or nocombining buffer ubufsize 8 # number of uncache buffer entries --- 105,111 ---- ! ##### Uncached Buffer Parameters ##### ubuftype comb # combining or nocombining buffer ubufsize 8 # number of uncache buffer entries *************** *** 187,192 **** --- 187,194 ---- ##### Main Memory Controller Parameters ##### mmc_sim_on 1 # enable detailed memory simulation + # alternative name: mmc_sim + # alternative values: fixed, pipelined, detailed mmc_latency 20 # fixed latency if detailed sim. is turned off mmc_frequency 1 # memory controller frequency relative to CPU mmc_debug 0 # enable debugging output Index: src/Memory/mmc_debug.c =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/src/Memory/mmc_debug.c,v retrieving revision 1.3 retrieving revision 1.4 diff --context -r1.3 -r1.4 *** src/Memory/mmc_debug.c 2002/10/25 20:25:14 1.3 --- src/Memory/mmc_debug.c 2002/11/25 17:13:40 1.4 *************** *** 137,143 **** YS__logmsg(nid, "Arbwaiters_count = %d\n", pmmc->arbwaiters_count); DumpLinkQueue("arbwaiters", &(pmmc->arbwaiters), 0x62, nid); ! if (mparam.sim_on == 0) { DumpLinkQueue("wait list", &(pmmc->waitlist), 0, nid); if (IsScheduled(pmmc->pevent)) --- 137,143 ---- YS__logmsg(nid, "Arbwaiters_count = %d\n", pmmc->arbwaiters_count); DumpLinkQueue("arbwaiters", &(pmmc->arbwaiters), 0x62, nid); ! if (mparam.sim != MMC_SIM_DETAILED) { DumpLinkQueue("wait list", &(pmmc->waitlist), 0, nid); if (IsScheduled(pmmc->pevent)) Index: src/Memory/mmc_init.c =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/src/Memory/mmc_init.c,v retrieving revision 1.5 retrieving revision 1.6 diff --context -r1.5 -r1.6 *** src/Memory/mmc_init.c 2002/10/25 20:25:14 1.5 --- src/Memory/mmc_init.c 2002/11/25 17:13:40 1.6 *************** *** 111,117 **** ptrans++; } ! if (mparam.sim_on == 0) { dqueue_init(&(pmmc->reqqueue), BUS_TOTAL_REQUESTS * 2); lqueue_init(&(pmmc->waitlist), BUS_TOTAL_REQUESTS * 2); --- 111,117 ---- ptrans++; } ! if (mparam.sim != MMC_SIM_DETAILED) { dqueue_init(&(pmmc->reqqueue), BUS_TOTAL_REQUESTS * 2); lqueue_init(&(pmmc->waitlist), BUS_TOTAL_REQUESTS * 2); *************** *** 144,156 **** /* * Some switches */ ! mparam.sim_on = 1; mparam.latency = 20; mparam.frequency = 1; mparam.debug = 0; mparam.collect_stats = 1; mparam.max_writeback_count = ARCH_cpus + ARCH_coh_ios; ! get_parameter("MMC_sim_on", &mparam.sim_on, PARAM_INT); get_parameter("MMC_latency", &mparam.latency, PARAM_INT); get_parameter("MMC_frequency", &mparam.frequency, PARAM_INT); get_parameter("MMC_debug", &mparam.debug, PARAM_INT); --- 144,170 ---- /* * Some switches */ ! mparam.sim = MMC_SIM_DETAILED; mparam.latency = 20; mparam.frequency = 1; mparam.debug = 0; mparam.collect_stats = 1; mparam.max_writeback_count = ARCH_cpus + ARCH_coh_ios; ! ! /* parameter name has been abbreviated, old name is still accepted */ ! /* also accepts old binary values (0/1) in addition to new textual values */ ! get_parameter("MMC_sim", buf, PARAM_STRING); ! if (strcmp(buf, "0") == 0) ! mparam.sim = MMC_SIM_FIXED; ! else if (strcmp(buf, "1") == 0) ! mparam.sim = MMC_SIM_DETAILED; ! else if (strncasecmp(buf, "fix", 3) == 0) ! mparam.sim = MMC_SIM_FIXED; ! else if (strncasecmp(buf, "pipe", 4) == 0) ! mparam.sim = MMC_SIM_PIPELINED; ! else if (strncasecmp(buf, "detail", 6) == 0) ! mparam.sim = MMC_SIM_DETAILED; ! get_parameter("MMC_latency", &mparam.latency, PARAM_INT); get_parameter("MMC_frequency", &mparam.frequency, PARAM_INT); get_parameter("MMC_debug", &mparam.debug, PARAM_INT); Index: src/Memory/mmc_main.c =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/src/Memory/mmc_main.c,v retrieving revision 1.6 retrieving revision 1.7 diff --context -r1.6 -r1.7 *** src/Memory/mmc_main.c 2002/11/01 20:30:49 1.6 --- src/Memory/mmc_main.c 2002/11/25 17:13:40 1.7 *************** *** 77,83 **** ptrans->c2c_copy = 0; req->memtrans = ptrans; ! switch (req->type) { case REQUEST: --- 77,83 ---- ptrans->c2c_copy = 0; req->memtrans = ptrans; ! switch (req->type) { case REQUEST: *************** *** 114,123 **** PID2BUS(pmmc->nodeid)->write_flowcontrol++; } ! if (mparam.sim_on == 0) ! MMC_nosim_start(pmmc, ptrans); ! else MMC_trans_enqueue(pmmc, ptrans); } --- 114,123 ---- PID2BUS(pmmc->nodeid)->write_flowcontrol++; } ! if (mparam.sim == MMC_SIM_DETAILED) MMC_trans_enqueue(pmmc, ptrans); + else + MMC_nosim_start(pmmc, ptrans); } *************** *** 288,294 **** /* * Used the the MMC simulator is turned off. In this case, each memory * access is serviced in a fixed latency (specified by mparam.latency in ! * terms of frequency cycles) and in FIFO order. */ void MMC_nosim_start(mmc_info_t *pmmc, mmc_trans_t *ptrans) { --- 288,294 ---- /* * Used the the MMC simulator is turned off. In this case, each memory * access is serviced in a fixed latency (specified by mparam.latency in ! * terms of frequency cycles) and in FIFO order. */ void MMC_nosim_start(mmc_info_t *pmmc, mmc_trans_t *ptrans) { *************** *** 319,324 **** --- 319,326 ---- mmc_info_t *pmmc = YS__ActEvnt->uptr1; mmc_trans_t *ptrans = YS__ActEvnt->uptr2; REQ *req = ptrans->req; + rsim_time_t delay; + if (--pmmc->trans_count == 0) { *************** *** 344,361 **** mmc_trans_t *new_trans; lqueue_get(&(pmmc->waitlist), new_trans); pmmc->pevent->uptr2 = new_trans; ! schedule_event(pmmc->pevent, ! YS__Simtime + (mparam.latency * mparam.frequency)); } if (ptrans) MMC_dram_done(pmmc->nodeid, ptrans); } /* * Used by DRAM backend. */ int MMC_sim_on(void) { ! return mparam.sim_on; } --- 346,371 ---- mmc_trans_t *new_trans; lqueue_get(&(pmmc->waitlist), new_trans); pmmc->pevent->uptr2 = new_trans; ! ! if (mparam.sim == MMC_SIM_FIXED) ! delay = (mparam.latency * mparam.frequency); ! ! if (mparam.sim == MMC_SIM_PIPELINED) ! delay = new_trans->issued - YS__Simtime + ! (mparam.latency * mparam.frequency); ! schedule_event(pmmc->pevent, YS__Simtime + delay); } if (ptrans) MMC_dram_done(pmmc->nodeid, ptrans); } + + /* * Used by DRAM backend. */ int MMC_sim_on(void) { ! return (mparam.sim == MMC_SIM_DETAILED); } Index: src/Memory/mmc_param.h =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/src/Memory/mmc_param.h,v retrieving revision 1.4 retrieving revision 1.5 diff --context -r1.4 -r1.5 *** src/Memory/mmc_param.h 2002/10/25 20:25:14 1.4 --- src/Memory/mmc_param.h 2002/11/25 17:13:40 1.5 *************** *** 64,70 **** typedef struct { /* Switches */ ! int sim_on; int latency; int frequency; int debug; --- 64,70 ---- typedef struct { /* Switches */ ! int sim; int latency; int frequency; int debug; *************** *** 74,78 **** --- 74,82 ---- } mmc_param_t; extern mmc_param_t mparam; + + #define MMC_SIM_FIXED 1 + #define MMC_SIM_PIPELINED 2 + #define MMC_SIM_DETAILED 3 #endif Index: src/Memory/mmc_stat.c =================================================================== RCS file: /res/impulse/users/map/cvsroot/ml-rsim/src/Memory/mmc_stat.c,v retrieving revision 1.4 retrieving revision 1.5 diff --context -r1.4 -r1.5 *** src/Memory/mmc_stat.c 2002/10/25 20:25:14 1.4 --- src/Memory/mmc_stat.c 2002/11/25 17:13:40 1.5 *************** *** 124,132 **** { YS__statmsg(nid, "Memory Controller Configuration\n"); ! if (mparam.sim_on == 0) { ! YS__statmsg(nid, " simulator \t Off (simulating fixed latency)\n"); YS__statmsg(nid, " latency \t%4d memory controller cycles\n", mparam.latency); YS__statmsg(nid, " frequency\t%4d\n", --- 124,141 ---- { YS__statmsg(nid, "Memory Controller Configuration\n"); ! if (mparam.sim == MMC_SIM_FIXED) { ! YS__statmsg(nid, " simulator \t Off - simulating fixed latency\n"); ! YS__statmsg(nid, " latency \t%4d memory controller cycles\n", ! mparam.latency); ! YS__statmsg(nid, " frequency\t%4d\n", ! mparam.frequency); ! } ! ! if (mparam.sim == MMC_SIM_PIPELINED) ! { ! YS__statmsg(nid, " simulator \t Off - simulating fixed, pipelined latency\n"); YS__statmsg(nid, " latency \t%4d memory controller cycles\n", mparam.latency); YS__statmsg(nid, " frequency\t%4d\n",