Accelerator Architecture Design:

Moore's law tell us that  we can integrate more and more transistors onto a chip.  This does not guarantee a commensurate increase in performance.  One solution is the recent trend towards heterogeneous multi-core. In addition to general purpose cores like the x86, one can embed a sea of accelerator cores that  increase the performance while improving the energy characteristics of the complete system.  My research explores an architectural methdology for the design of programmable
accelerator architectures for niche application domains.  Our CASES paper talks about the design of such an "ASIC-like" architecture for face recognition.  

Interconnect Aware Compilation:

    A key ingredient to the performance, power, and programmable advantages of  "ASIC-like" architectures is exposing the interconnect  completely to the compiler.  Exposing wire properties like
delay, bandwidth, and routability helps in achieving high performance at low power dissipation.  One critical side-effect is that it also preserves the programmability of the system.  More information on  interconnect aware compilation and it benefits can be found here.