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- Ph.D. (Computer Science), School of Computing,
University of Utah, 2003 - Current
- M.E., Electrical and Computer Engineering,
University of Utah, 2003
- B.E., Department of Electronics and Communication, M J College of Engineering and Technology,
Osmania
University, 2000
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- Data Flow Architectures
- Hardware for Ray Tracing algorithms
- Asynchrony in Computer Processor Architecture
- Asynchronous VLSI Circuits
- I was involved in developing CMOS standard cell libraries for use with the Cadence and Synopsys CAD tool sets. A few classes use these libraries at University of Utah — CS6710: Digital VLSI Design & CS6830: VLSI Architecture
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| Employment and Experience |
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Design Engineer - Intel Corporation [Jan 2007 - current]
Graduate Intern - Technology Integration Group, Intel Corporation [May 2007 - Jan 2007]
- Developed a fully automated timing correlation utility
(delay, setup/hold time) for Quality Analysis of standard cell
libraries (perl and tcl).
- Developed a tool which compares characterization data from
various data sources (standard cell libraries and several
in-house tool reports) and displays results in graphical format
(perl and gnuplot).
Graduate Intern - CT Labs, Intel Corporation [Jan 2006 - May 2006]
- Worked on a next generation Ethernet controller prototype.
- RTL (VHDL) code writing, debug and validation both in the simulation test environment.
- Built a random test generation validation environment for validating the RTL using Specman e language.
- Debug and validation of the FPGA prototype.
Research Assistant - School of Computing, University of Utah [Summer 2003 - Summer 2007]
- Working on the dataflow architecture approach for raytracing hardware
- Working on optimizing multiprocessor architectures for efficient implementation of ray-tracing algorithms
- Built VLSI circuit systems which were used as comparable examples with the ARCS - an architectural level asynchronous communication event based simulator
- External support for the course VLSI Architecture
- External support for the course Digital VLSI Design
University Teaching Assistant (UTA) - School of Computing, University of Utah [Summer 2004 - Spring 2005]
- Awarded the UTA grant for the year 2004-2005
- Developed CMOS Standard Cell Libraries for use with the Cadence and Synopsys tool sets. These libraries are being used in classes at University of Utah - Digital VLSI Design and VLSI Architecture
- External support for the course VLSI Architecture
- External support for the course Digital VLSI Design
Graduate Teaching Assistant - School of Computing & Electrical and Computer Engineering, University of Utah
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