Dissertation: FPGA Based Digital Signal Processing-Study of
An Adaptive Echo canceler.
Experience
AMD Inc, Discrete Graphics Division (GPU).
-- January 2007-Present
Power estimation: from spreadsheet to netlist. Power optimization:
System, Architecture, Micro-architecture, RTL, netlist. Power management: runtime power management.
I am also leading the PowerRed
development. PowerRed is an "Architecture level power modeling
infrastructure". You can refer to my publications for more details.
Post-Doctoral Researcher at Siemens TTB and Co-founder of Satva Design Automation
-- June 2005-December 2006
High Performance Low Power Embedded Processors
Research Assistant, School of
Computing--Prof. Al Davis Summer 2003-May 2005
ACT
Processor
I proposed a high performance, low-power, yet
flexible coprocessor for wireless applications.
Research Assistant, School of
Computing--Prof. Al Davis Spring 2003-Summer
2003
The perception Processor
I worked on the design and
implementation of a high performance, low-power perception processor.
Research Assistant, School of
Computing--Prof. John Carter Fall 2000-Fall 2002
Micro Architecture and VLSI
for an Adaptive High Performance Memory Controller
I showed
that the
performance of SDRAM-based memory system can be improved by
Memory Controllers that intelligently schedule multiple
requests and take advantage of bank parallelism available
within the SDRAM chips. Furthermore, the improvement can be
achieved with a small increase in chip area
Intern, Ericsson
Telecommunication, Rome,Italy--Eng. C. Porfiri Fall
1998-Summer 1999
FPGA-based digital signal processing-Study
of an adaptive echo canceler.
The scope of the work was
the evaluation of Programmable Logic in comparison with
digital signal processors when the algorithms require high
computing power per device.
Research: ACT
Please refer to the research page. This was part of
my PhD research and it has not been update it for sometime.
Advance Computer Architecture ℘℘ CAD of Digital Circuits ℘℘ Embedded Systems
Parallel Computer Architecture ℘℘ Analog Circuits Design I ℘℘ Analog
Circuits Design II
VLSI Architecture ℘℘ Advance DSP I
Seminars:
High Performance Memory systems ℘℘ Networking ℘℘
Asynchrounous Circuits
Courses at Haas Business School, University of California Berkeley
New Venture Finance (Audit): Start-up Organization
Wireless Communication: Analysis of the Industry Structure, The Value Chain,
The Business Model, The Role of Regulation and Oppurtunities for Start-ups and
New Entrants.
Other Activities
Reviewer for IEEE International Conference on Sensor and Ad hoc Communications and Networks
Reviewer for Internation Journal in Computer Networks (COMNET)
Reviewer for ACM Multimedia
Reviewer for ACM/SPIE Multimedia Computing and Networking (MMCN)
Reviewer for the Journal of Systems and Software (elsevier)
Supervised a PhD candidate from the school of computing, University of Utah,
during his summer internship at AMD, May/2007 to September/2007