PowerView is a collection of several digital design tools manufactured by ViewLogic. Among the tools used in the RPT-project were:

• ViewDraw - a graphical based design tool mainly used for interconnecting several component symbols into a schematic.

• ViewSynthesis - a command line based tool used for synthesizing ViewLogic VHDL code into a specific gate technology. Does not currently (spring 1995) support IEEE VHDL.

• ViewPartitioner - a command line based tool used for partitioning of a design into multiple FPGA's. Does not currently (spring 1995) support Orca FPGA' s from AT&T.

• ViewSim - a command line based tool for simulating a design. Supports communication to ViewDraw which makes it possible to visualize the vectors graphically in the schematic design. Supports compiled simulation, clock generation and batch file simulation.

Several other tools are also available for PowerView.