UART Receiver

A UART (Universal Asynchronous Receiver/Transmitter) is a circuit that performs serial data communication between two different circuits. The UART consists of two main circuits, a sender circuit and a receiver circuit. The reason we only have a receiver is because we only needed input from the keyboard, we did not need to send data to the terminal as output because we decided to do other forms of output.

Our UART receiver consists of four circuits; the receiver circuit that contains the receiver control unit and the data path elements, a clock divider circuit which is used to step down the system clock, and the handshake circuit. At first we wrote the control unit for the receiver with VHDL but could not get it to simulate correctly. So we redid the control unit the hard way with Veiwdraw.

§ Receiver

The receiver consists of a Finite State Machine (FSM), counters, and a shifter. The FSM receives data from the RCV line, the ACK signal from the handshake, and from the counter. With the data received from these sources, it controls when to start and stop receiving bits from the Data Terminal Equipment (DTE). It also controls when to raise and lower the REQ signal. The counters receive signals from the FSM so they would start and stop counting at the right time. The shifter is controlled by the FSM so it receives the correct data from the RCV line.

§ Clock Divider

The clock divider divides the system clock from 50MHz to 76.8 kHz, which is 8 times faster than the baud rate of the DTE.

§ Handshake

The handshake gets the REQ signal from the receiver and the DONE signal from the computer processor and sends the ACK signal to the receiver in order to acknowledge when the receiver can start to receive a new byte.

How our processor communicates with the UART receiver:

The processor communicates with the UART receiver thru load and store instructions. To read data from the receiver the processor must put the address of the receiver -0xFFFF in a register and then perform a load operation from that address. The data from the receiver is then loaded into the register specified during the load operation. The DONE bit is bit 8, and bits 7 - 0 contain the data from the receiver. If bit 8 is equal to‘1’ then the data is new. If bit 8 is equal to ‘0’ then the receiver does not contain fresh data. To send the DONE signal to the receiver so that it will collect more data the processor must perform a store to address 0xFFFD, the data sent to that address will be ignored, it is only the store operation to address 0xFFFD that raises the DONE signal. The circuit input shows how we integrated the UART receiver into memory space. The circuit output shows how the store instruction sets the DONE signal high.