We report on our efforts to design faster circuits for floating-point division and square root operations. Unlike addition, subtraction, and multiplication, these operations seem to be more difficult because there is no clear way to break the problem up into many pieces that can be processed in parallel; all effective approaches seem to require an iterative sequence of steps, in which computational phases alternate with critical decision points.
Speculative parallelism can improve speed by overlapping computational phases with decision points and each other. The central idea is to launch a computational step before its controlling decision has occurred by launching several copies of the computation, one for each possible result of the decision (typically a decision about what should be the next digit of the quotient). The decision point later selects among the results, rather than selecting which step to perform next. The "wasted" effort of computing results that are eventually discarded is the cost paid for the increase in speed.
This strategy was used Prabhu and Zyner to speed up SRT division and square root for Sun's UltraSPARC microprocessor. The research described in this talk pushes the technique even further, gaining about another factor of two in speed, at the expense of requiring substantially more silicon.
Friday, March 26 1999
3:30pm
104 Engineering and Mines Classroom Building
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