Digital VLSI Chip Design
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UofU_Analog_Parts

Please note that all this information is provided "as is" and without any warranty of any kind. Please use the information at your own risk. This warning is especially true of the cell libraries!

This is a small library that contains transistor cells (nmos and pmos) copied from the NCSU_Analog_Parts library. The NCSU versions have zero delay when simulated with a Verilog simulator. The UofU versions have been modified to have 0.1 units of delay when simulated using Verilog. I find that this makes a much more realistic simulation and can help spot certain types of delay issues in the circuit. You do have to beware, however, of forgetting that this is an abstract "unit delay" type of simulation and thinking of this in ns. It's not!

The UofU_Analog_Parts library now comes in two flavors: CDB for use with Cadence IC v5, and OA for use with Cadence IC v6

• IC v5 (CDB) version: UofU_Analog_Parts.tar.gz
• ICv6 (OA) version: OA_UofU_Analog_Parts.tar.gz

To use, uncompress and untar the UofU_Analog_Parts library from the gzipped tar file. Put that directory somewhere where people can access it, and then point to it in your cds.lib file. You can put this in the NCSU CDK cds.lib file in $CDK_DIR/cdssetup/cds.lib, or in the $LOCAL_CADSETUP/cadence/cds.lib file, or in the cds.lib file that is in the directory from which you start the Cadence tools. The format in the cds.lib file is:

DEFINE UofU_Analog_Parts <path-to-the-directory>/UofU_Analog_Parts

The cells defined in UofU_Analog_Parts are (see section 4.4.4 in the book for more details):

• nmos and pmos - basic three-terminal transistors that have 0.1 units of delay when simulated in Verilog. The source connection is the one with the arrow and should be connected to the power supply (either vdd (pmos) or gnd (nmos). The connection without the arrow is the drain and is the "output" of the device.
  
  
• bi_nmos and bi_pmos - three-terminal transistors that operate in a bidirectional fashion, and with 0.1 units of delay, when simulated with a Verilog simulator. The regular nmos and pmos cells are unidirectional - the drain connection is the "output."These bidirectional versions aren't typically needed, and will slow down the simulation, but if you are using a transistor as a true bidirecional pass gate, these are what you need. Note that you don'tneed these for a unidirectional pass gate, but you're making a transmission gate, make sure that the drains of both transistors are connected to the transmission gate's output
  
  
• r_nmos and r_pmos - three-terminal transistors that operate as "resistive" (weak) devices, and with 0.1 units of delay, when simulated with a Verilog simluator. These are what you want if you are making a weak-feedback storage device of some sort, for example. To netlist correctly, make sure that the simVerilogHandleSwitchRCData variable is set in the simulator. You can do this in the options of Verilog-XL or NC_Verilog, or put the following line in your .simrc file:
  
  simVerilogHandleSwitchRCData = 't

See the UofU-modified simrc file for an example: here are links to the OA and CDB versions (they're not much different)

Last modified May 18, 2011.