################################################
#  Encounter Input configuration file          #
#  Erik Brunvand, University of Utah           #
################################################
global rda_Input
#
#########################################################
# Here are the parts you need to update for your design
#########################################################
#
# Your input is structural verilog. Set the top module name 
# and also give the .sdc file you used in synthesis for the 
# clock timing constraints. 
set rda_Input(ui_netlist)        {../mips_struct.v}
set rda_Input(ui_topcell)        {mips}
set rda_Input(ui_timingcon_file) {../mips_struct.sdc}
#
# Leave min and max empty if you have only one timing library
# (space-separated if you have more than one)
set rda_Input(ui_timelib)        {UofU_Digital_v1_2.lib}
set rda_Input(ui_timelib,min)    {}
set rda_Input(ui_timelib,max)    {}
#
# Set the name of your lef file or files 
# (space-separated if you have more than one). 
set rda_Input(ui_leffile) {UofU_Digital_v1_2.lef}
#
# Include the footprints of your cells that fit these uses. Delay 
# can be an inverter or a buffer. Leave buf blank if you don't 
# have a non-inverting buffer. These are the "footprints" in 
# the .lib file, not the cell names. 
set rda_Input(ui_buf_footprint)      {buf}
set rda_Input(ui_delay_footprint)    {buf}
set rda_Input(ui_inv_footprint)      {inv}
set rda_Input(ui_cts_cell_footprint) {inv}
#
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