DEVYANI GHOSH

M.S. (Thesis) in Computer Science, Fall 2008 (expected)
School of Computing, University of Utah
Advisor: Prof. John Carter.

B.Tech in Electrical and Electronics Engineering, May 2004
National Institute of Technology, Tiruchirapalli, India

It is exciting to be in the emerging multicore era that brings in game changing opportunity in processing performance and power efficiency, while demanding new design and programming challenges. My research interests are primarily centered around computer architecture with emphasis on high performance memory subsystems. While I am fascinated by several areas in computer systems research, I have recently developed keen interest in machine learning, algorithms and data mining.

I work with John Carter to investigate techniques to hide long memory latencies in Chip Multiprocessors (CMPs) by means of prediction and speculation.  My research focus is on applying machine learning techniques for accelerating cache coherence protocol operations. Thanks to Hal Daume (to whom I blame most of my interest in machine learning) for his incredible support throughout my work.

Refereed Publications:

I am a second year graduate student at University of Utah. Prior to coming to Salt Lake City, I spent two exciting years as a software engineer at  STMicroelectronics, India  (July 2004 - July 2006). I earned my undergraduate major in Electrical and Electronics Engineering from National Institute of Technology, Trichy, India in May 2004.

I was born in the beautiful valley of Dehradun, and spent my childhood growing up in St. Joseph's Academy, Dehradun (from Kindergarten to Class XII)