Bharat
Chandramouli
761 San Pablo
Ave, Sunnyvale, CA 94085 408-242-5040,
cbharat@gmail.com
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Summary ·
Experienced in
designing efficient algorithms & data structures for verification of large-scale
chip designs that have hundreds of millions of gates and nets connecting
them. ·
Strong
mathematical and analytical problem solving skills. Education Master of Science in Computer
Science (GPA
3.83/4) Master of Science (Honors) in
Mathematics (Core
GPA: 9.16/10.00; Overall GPA: 8.27/10.00)
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Experience Cadence
Design Systems, San Jose, California Senior Member of Technical Staff June 03 – April 05 ·
Verification of low power
intent and implementation of digital ASIC chips o
Implemented algorithms to
verify consistency and completeness of specification of low power intent ·
Parser for the Common Power
Format (CPF) Language o
Implemented a tcl-based parser
for Common Power Format (CPF) Language. o
Parser shared by all product
groups in Cadence & distributed externally
[http://www.eetimes.com/showArticle.jhtml?articleID=196901656] o
Participated in the design of
the language which provides a formal way to describe low power techniques
used in digital chip design. ·
Automatic Logic Synthesis of
Low Power Cells o
Implemented low power logic
insertion framework including isolation, level shifter & state retention
logic insertion. o
Demonstrated how the low power
logic inserted into the design can be leveraged for the verification of low
power intent [2 patents submitted] ·
Parser and elaborator for the
VHDL language o
Full responsibility for parser
for VHDL, a strongly typed hardware description language o
Supported function and operator
overloading, user defined types, package linking and namespaces o
Implemented hierarchical and
nested configurations to allow flexible instance linking o
Implemented arena-based memory
allocation to improve memory efficiency Verplex Systems, Milpitas, California |
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Member of Technical
Staff September 01 – June 03
[Cadence
acquired Verplex in June 03] ·
Hardware Description Language
Dependency Analysis o
Design a bytecode format to
store/load the design information on disk to minimize memory consumption o
Implemented a bytecode-based
defs/uses algorithm to provide source-level loads and drivers tracing o
Implemented connectivity-based
dependence analysis at design instance level ·
Source Code Value Annotation o
Implemented simulation package
for doing local source-level event-driven simulation on bytecode o
Hierarchical simulation package
for simulation across module instances o
Dynamic dependency analysis to
display only active drivers/loads University
of Utah, Salt Lake City, Utah Research assistant,
Impulse Group Aug 99 – June 01 ·
As part of my
Master's thesis research, I worked on the problem of compiler optimization
guidance for a certain class of optimizations known as restructuring
optimizations. These optimizations increase the spatial locality of array
references to improve cache hierarchy performance. I devised methods to
automatically decide which optimization(s) to apply, given a set of competing
software and hardware-based restructuring optimizations. The software based
optimization techniques include array restructuring & loop
transformations; the hardware-based technique called remapping-based
restructuring is an optimization that exploits hardware support for address
remapping from a smart memory controller. I have studied several benchmark
programs and optimized them. I have gained an in-depth understanding of
computer architecture, and its interaction with compiler optimizations. Microsoft
Corporation, Redmond, Washington Software
Design Engineer Intern May 99 –
Aug 99 ·
I developed a
meta-travel search engine in C++ that extracted the lowest flight prices, for
any itinerary, of Expedia and its leading competitors. Wipro
Global R&D, Bangalore, India Software
Engineer ·
Worked on the
UWIN (UNIX for WINdows) project of AT&T Research. UWIN
provides a UNIX environment on Windows. ·
Implemented a
terminal emulation driver using Win32 API to provide an emulation of the vt100
terminal. I also wrote the SCSI Tape emulation driver for UWIN in Windows NT
that let UNIX code control the Windows tape drive from within UWIN using
ioctl() calls. Cadence
Design Systems, Noida, India Software Engineer
Intern Jan 96 – May 96 ·
Wrote Perl
scripts for analyzing performance of the Cadence Synergy tool. ·
Implemented a
HTML report editor that could be used to generate weekly status reports. ·
Implemented a
proactive password checker that checked and disallowed obviously weak passwords,
and provided for password aging. Skills C/C++ [expert], Unix/Linux
[expert], tcl [expert], lex & yacc [strong], Java [fair], Perl [good],
Python [rookie] Publications CPF-based Hierarchical
Design Analysis & Integration
Design Considerations
and Applications of the Common Power Format
A Cost Model for
Integrated Restructuring Optimizations Journal
of Instruction-Level Parallelism (JILP), August 2003 A Cost Framework for
Evaluating Integrated Restructuring Optimizations International
Conference on Parallel Architectures and Compilation Techniques (IEEE-PACT) , Sept 2001 Memory System Support for Dynamic Cacheline
Assembly. Proceedings of the Second Workshop on
Intelligent Memory Systems, Nov. 2000. Honors and Awards ·
Six
Instant Recognition
Awards
from
peers ·
Cadence
Front End Division
Award
for
Q1 2008 ·
Cadence
Excellence in
Innovation Award
for
2006 ·
Cadence
Products & Technology Division Level Award for 1H2006 ·
Third Place in Utah Entrepreneur
Challenge, 2000 a state level business plan competition for college students ·
First Place, Inter-Collegiate
Mathematics Olympiad, APOGEE 1996 ·
Top 0.1%, Mathematics, All
India Senior Secondary Examination, 1992 ·
Secured
rank in the top 2% in the Entrance Examination for IIT-JEE
’92 |