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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| Combinational_Logic/ | 28-Oct-2008 15:02 | - | |
| Gate_Optimization/ | 28-Oct-2008 15:02 | - | |
| Layouts/ | 28-Oct-2008 15:02 | - | |
| Logical Effort.ppt | 23-Sep-2008 12:12 | 848K | |
| Low_Power/ | 21-Dec-2008 00:10 | - | |
| MIPS_uP/ | 28-Oct-2008 15:03 | - | |
| NoC_Routing/ | 28-Oct-2008 15:03 | - | |
| Other_Libraries/ | 24-Dec-2008 17:45 | - | |
| Other_Projects/ | 28-Oct-2008 15:04 | - | |
| Sequential Circuit Timing.pdf | 02-Sep-2008 14:01 | 2.9M | |
| Timing Fundamentals.ppt | 02-Sep-2008 16:08 | 2.6M | |
| VLSI_MIPS.tar.bz2 | 24-Dec-2008 17:48 | 1.5M | |
| Verilog Codes/ | 28-Oct-2008 15:05 | - | |