I have been designing asynchronous circuits and systems for most of my professional career. The current focus is on automatic synthesis tools capable of generating correct by construction high performance circuits from relatively conventional finite-state machine oriented specifications.
The basis of this work was the development of a restricted version of multiple input change circuit synthesis techniques called burst mode. The result of this CAD phase has been the creation of two tool kits MEAT and STETSON.
MEAT (for Most Excellent Asynchronous Tool - a blatant ripoff from a movie title) takes finite state machine specifications and generates highly optimized complex-gate CMOS transistor schematics. This tool kit was used to develop a high performance multicomputer router chip known as the Post Office . The Post Office is a 300,000 transistor device and was used for the interconnect fabric of the HP Mayfly multiprocessor prototype.
The downside of the MEAT tool was that it required hand layout of the synthesized schematic. This led to the development of STETSON.
MEAT was developed with Ken Stevens and Bill Coates while we were all members of the research staff at Hewlett-Packard Laboratories.
STETSON extended the MEAT idea but rather than being a standalone tool, STETSON is integrated into the MENTOR VLSI design tool suite. Rather than trying to solve the difficult problem of generating optimized complex gate circuits, STETSON bases its final implementation on standard cell technology and uses MENTOR's AUTOCELL for place and route.
This work was done at the HP Stanford Science Center with a number of colleagues. In particular the work of: Alan Marshall, Jeremy Gunawardena, Bill Coates, David Dill, Theresa Meng, Steve Nowick, Polly Siegel, and Ken Yun.