Al Davis

Professor &  Director
School of Computing
University of Utah

Work Address:
Al Davis
School of Computing
50 S. Campus Drive, Room 3190
Salt Lake City, Utah 84112-9205
Voice: (801) 581-3991
Fax: (801) 581-5843
Email:  my id_name is ald and my email is

Potential Graduate Students (please read)

I no longer answer direct email from students expressing interest in our graduate program, or about my interest in supporting you if you decide to come here to study.  There are just too many requests for me to answer individually.  If you are qualified, you should apply.  If you get accepted and show prowess in a research area then you'll get supported.  Matching interests and exploring a research fit in my area will happen after you are here.  There is a  button to the department's web page at the bottom of this page, click on it and you can find on-line application materials as well as detailed information on our program and the associated requirements.

Current Research Interests

Traditionally I have worked in the areas of high performance computer architecture, asynchronous circuits and systems, VLSI, embedded systems, domain specific hardware accelerator synthesis tools, and parallel computation.   While I still maintain an interest in these disciplines, my current research focus is on energy efficient architectures, main memory interfaces and microarchitecture, warehouse-scale interconnection networks, hardware support for high-performance ray tracing, and silicon nanophotonics.  The silicon nanophotonics work is in collaboration with colleagues at HP Laboratories in Palo Alto, CA.

I am part of the Utah Architecture Group (a.k.a. Utah Arch) - follow this link to a description of current projects, publications, etc.  The publications that can be found here cover my current research interests at Utah. 

Utah Arch logo

Course Materials

In the recent past I have taught embedded systems (CS 5780), computer architecture (CS 6810), and computer systems (CS 4400).  Current course materials for these courses can be found at - where xxxx is the appropriate course number.  

Now, as Director of the School of Computing, I am only teaching the computer engineering senior project courses: CS 3992 & CS 4710

Selected Other Recent Publications (which don't also appear in Utah Arch)

o J-H Ahn, N. Binkert, A. Davis, M. McLaren, N. Muralimanohar.  The Role of Optics in High-Radix Switch Design.  To appear in ISCA 2011.
o J-H Ahn, R. G. Beausoleil, N. Binkert, A. Davis, M. Fiorentino, N. P. Jouppi, M. McLaren, M. Monchiero, N. Muralimanohar, R. S. Schreiber, D. Vantrease.  CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study.  Chapter 9 in Low Power Networks on Chip, Springer, October 2010.
o G. B. P. Bezerra, S. Forrest, M. Moses, A. Davis, P. Zarkesh-Ha.  Energy Prediction in NOC using Rent's Rule Communication Probability Distribution.  SLIP, June 2010.
o N. Binkert, A. Davis, M. Lipasti, R. S. Schreiber, D. Vantrease.  Nanophotonic Barriers.  PICA, December 2009.
o J-H Ahn, N. Binkert, A. Davis, M. McLaren, R. S. Schreiber.  HyperX: Topology, Routing, and Packaging of Efficient Large-Scale Networks.  Supercomputing, November 2009.
o J-H Ahn, M. Fiorentino, R. G. Beaausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, Q. Xu.  Devices and architectures for photonic chip-scale integration.  Journal of Applied Physics A, Vol. 95(4), June 2009.
o K. Ramani, C. Gribble, A. Davis.  StreamRay: A Stream Filtering Architecture for Coherent Ray Tracing.  ASPLOS, March 2009.
o M. Moses, S. Forrest, A. Davis, J.H. Brown, M. Lodder.  Scaling Theory for Information Networks.  Journal of the Royal Socieity Interface, Vol. 5(29), December 2008.
o R. G. Beausoleil, J-H Ahn, N. Binkert, A. Davis, D. Fattal, M. Fiorentino, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, Q. Xu.  A Nanophotonic Interconnect for High-Performance Many-Core Computation.  Hot Interconnects, Aug. 2008.
o D. Vantrease, R. S. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, J-H Ahn.  Corona: System Implications of Emerging Nanophotonic Technology.  ISCA, June 2008.
o K. Ramani, A. Davis.  Application Driven Embedded System Design.  A Face Recognition Case Study.  CASES, October 2007.

Selected Older Publications
o L. Schelicke, A. Davis.  Design Trade-Offs for User Level I/O Architectures.  IEEE Transactions on Computers, Vol. 55(8), August 2006.
o A. Ibrahim, A. Davis, M. Parker.  ACT: A Low-Power VLIW Co-Processor for DSP Applications.  CODESS, July 2005.
o B. Mathew, A. Davis.  A Low-Power Architecture for Embedded Perception.  CASES, October 2004.
oA. Davis, U. Prestor. An Application Centric CC-Numa Profiler.  Proceedings of the IEEE Workshop on Workload Characterization IV, December 2001.
o A. Davis, Lamber Schaelicke, Sally McKee.  Profiling Interrupts in Modern Architectures.  Proceedings of the Eighth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems (MASCOTS-2000), IEEE CS Press,  pp. 70-79, August 2000.
o A. Davis, B.K. Mathew, S.A. McKee, J.B. Carter.  Design of a Parallel Vector Access Unit.  Proceedings of the Sixth International Symposium on High Performance Computer Architecture (HPCA-6), pp. 39-48, January 2000.
o A. Davis, B.K. Mathew, S.A. McKee, J.B. Carter.  Algorithmic Foundations for a Parallel Vector Access Memory System.  Proceedings of the 12th ACM Symposium on Parallel Algorithms and Architectures, July 2000.
o A. Davis, J.B. Carter, W.C. Hsieh, L.B. Stoller, M.R. Swanson, L. Zhang,  S. A. McKee. Impulse: Building a Smarter Memory Controller.  Proceedings of the Fifth International Symposium on High Performance Computer Architecture (HPCA-5), pp. 70-79, January 1999.
o A. Davis,  J. Carter, W. Hsieh, M. Swanson, L. Zhang, M. Parker, L. Schaelicke, L. Stoller, T. Tateyama.  Memory System Support for Irregular Applications.  Proceedings of the Fourth Workshop on Languages, Compilers, and Run-time Systems for Scalable Computers.  May 1998.
o A. Davis, M. Swanson, M. Parker. Efficient Communication Mechanisms for Cluster Based Parallel Computing. Springer-Verlag Lecture Notes in Computer Science #1199, pp. 1-15, Feb. 1997. 
o A. Davis, Steven M. Nowick. An Introduction to Asynchronous Circuit Design. University of Utah Technical Report, UUCS-97-013, September 1997. [A version of this report appears in the Encyclopedia of Computer Science.]
o A. Davis, Synthesizing Asynchronous Circuits: Practice and Experience. Modern Asynchronous Design Practice, Springer-Verlag Workshops in Computer Science, Chapter 3,  pp. 104 - 150, edited by A. Davis and G. Birtwistle). April 1995.
oA. Davis, B. Coates, K. Stevens. Automatic Synthesis of Fast Compact Self-Timed Control Circuits. Proceedings of the IFIP Working Conference on Asynchronous Design Methodologies. Manchester, England; April 1993, pp. 193--208.
o A. Davis, B. Coates, K. Stevens. The Post Office Experience: designing a large asynchronous chip. Integration Vol. 15, No. 3, November 1993, pp. 341-366.

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