Al Davis

Professor &  Associate Director
Computer Science Department
University of Utah

NerdNerdDirtBikerSkier
Work Address:
Al Davis
School of Computing
50 S. Campus Drive, Room 3190
Salt Lake City, Utah 84112-9205
Voice: (801) 581-3991
Fax: (801) 581-5843
Email:  my id_name is ald and my email is id-name@cs.utah.edu

Potential Graduate Students

I no longer answer direct email from foreign students expressing interest in our graduate program, or about my interest in supporting you if you decide to come here to study.  There are just too many requests for me to answer individually.  If you are qualified, you should apply and if you get accepted then you'll get supported.  Matching interests and exploring a research fit in my area will happen after you are here.  There is a  button to the departments web page at the bottom of this page, click on it and you can find on-line application materials as well as detailed information on our program and the associated requirements.

Current Research Interests

Traditionally I have worked in the areas of high performance computer architecture, asynchronous circuits and systems, VLSI, and parallel computation.   While I still maintain an interest in these disciplines, my main academic focus has shifted to embedded systems.  In
particular the investigation of architectures and supporting design methodologies and tools which provide unprecedented levels of compute power per watt for important application domains.  The APES project is focused on perception and the ACT project is primarily concerned with future cellular telephony applications.  However both APES and ACT pursue similar architectural directions and essentually share the same design methodology and tool-kit.   I am also involved in a continuing effort called HPIO which continues to develop architectures that exhibit significant improvement in I/O performance.   Summaries and publications for each follow.

APES - Advanced Perceptive Embedded Systems

Ubiquitous computing is a a compelling vision.  However before we can expect to naturally interact with computing services that are invisibly embedded into our environment, natural human interfaces will be required.  The most obvious need is for speech and visual feature recognition.   The biggest problem is that even the best existing speech and visual feature recognizers are heavy-weight applications in the embedded space. They require higher performance than embedded systems can provide and often even performance microprocessors aren't sufficient.  The other problem is that performance processors consume too much power to be tractable in the embedded space.   We started out looking for ways to accelerate existing embedded processors with ASIC accelerators and have now settled on a much more general purpose cluster co-processor approach which has a performance/energy level that is similar to ASIC's while exhibiting much of the generality of convential processors but at a significant performance and energy improvement.

Binu Mathew is the lead student in this effort which forms the basis for his Ph.D. dissertation (completion expected: summer of 2004). Recent publications are:  

ACT - Architectures for Cellular Telephony

The growth rate in the complexity of cellular telephony algorithms is greater than Moore's law scaling rates.  The result that the existing architectures will not be able to support the new 3G and 4G telephony standards in even smaller and more energy efficient mobile packages.  The result is that ASIC's will be necessary to achieve the necessary performance/efficiency levels.  The problem however is that telephony algorithms and standards change rapidly and ASIC design cycles are both long and expensive.   The ACT project is investigating energy efficient yet computationally powerful embedded cluster coprocessor architectures which have performance/energy characteristics that are close to ASIC capabilities while retaining much of the generality of the software on processor approach.

Ali Ibrahim is the lead student in this effort which is the target of his Ph.D. dissertation (completion expected summer 2004).  Recent publications are:

HPIO - High Performance I/O Architectures

I/O performance is increasingly limiting computing performance in our modern highly interconnected, communication oriented, internet based world.   Lambert Schaelicke worked on the development of a simple yet very low overhead architecture to support User-Level I/O.    Mike Parker is working on utilizing SMT architecture techniques to effectively hide interrupt latencies and to create a class of I/O architectures that can be significantly more flexible and adaptive without sacrificing a significant level of performance.   Recent publications are:

Course Materials

These links will take you to a course syllabus which contains links that may be followed to get individual lecture slides, sample exams, exam solutions, etc. Note that my PostScript previewer doesn't do a very good job on some of these files - printing them works, but hopefully your previewer is infinitely better than mine and you'll avoid all that useless paper. Good luck. The original slides were done in FrameMaker and sources are available on request.  CS4400 slides are in Powerpoint and are based on course material from CMU, hence the source for these slides will not be distributed.

Other Selected Publications
Note - the .ps files print properly but don't preview well on my machines.

 
o A. Davis, U. Prestor. An Application Centric CC-Numa Profiler.  Proceedings of the IEEE Workshop on Workload Characterization IV, December 2001.
o A. Davis, Lamber Schaelicke, Sally McKee.  Profiling Interrupts in Modern Architectures.  Proceedings of the Eighth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems (MASCOTS-2000), IEEE CS Press,  pp. 70-79, August 2000.
o A. Davis, B.K. Mathew, S.A. McKee, J.B. Carter.  Design of a Parallel Vector Access Unit.  Proceedings of the Sixth International Symposium on High Performance Computer Architecture (HPCA-6), pp. 39-48, January 2000.
o A. Davis, B.K. Mathew, S.A. McKee, J.B. Carter.  Algorithmic Foundations for a Parallel Vector Access Memory System.  Proceedings of the 12th ACM Symposium on Parallel Algorithms and Architectures, July 2000.
o A. Davis, J.B. Carter, W.C. Hsieh, L.B. Stoller, M.R. Swanson, L. Zhang,  S. A. McKee. Impulse: Building a Smarter Memory Controller.  Proceedings of the Fifth International Symposium on High Performance Computer Architecture (HPCA-5), pp. 70-79, January 1999.
o A. Davis,  J. Carter, W. Hsieh, M. Swanson, L. Zhang, M. Parker, L. Schaelicke, L. Stoller, T. Tateyama.  Memory System Support for Irregular Applications.  Proceedings of the Fourth Workshop on Languages, Compilers, and Run-time Systems for Scalable Computers.  May 1998.
o A. Davis, M. Swanson, M. Parker. Efficient Communication Mechanisms for Cluster Based Parallel Computing. Springer-Verlag Lecture Notes in Computer Science #1199, pp. 1-15, Feb. 1997. 
o A. Davis, Steven M. Nowick. An Introduction to Asynchronous Circuit Design. University of Utah Technical Report, UUCS-97-013, September 1997. [A version of this report appears in the Encyclopedia of Computer Science.]
o A. Davis, Synthesizing Asynchronous Circuits: Practice and Experience. Modern Asynchronous Design Practice, Chapter 3, pp.104-150, Springer Verlag Workshops in Computer Science, edited by A. Davis and G. Birtwistle). April 1995.
oA. Davis, B. Coates, K. Stevens. Automatic Synthesis of Fast Compact Self-Timed Control Circuits. Proceedings of the IFIP Working Conference on Asynchronous Design Methodologies. Manchester, England; April 1993, pp. 193--208.
o A. Davis, B. Coates, K. Stevens. The Post Office Experience: designing a large asynchronous chip. Integration Vol. 15, No. 3, November 1993, pp. 341-366.

My login_id is ald, to send email send it to: login-id@cs.utah.edu
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