8:15 - 8:30	Opening Remarks
8:30 - 10:00	Keynote: John Edmondson, NVIDIA: Memory System Design Challenges for Future Generation GPUs
10:30 - 12:00	Session 1: Memory-Level Parallelism
	Are We Ready for High Memory-Level Parallelism? Luis Ceze, James Tuck, and Josep Torrellas University of Illinois at Urbana-Champaign MLP Exploitation with Seamless Preload Zhen Yang, Xudong Shi, Feiqi Su, and Jih-Kwon Peir University of Florida A Multi-Objective Integer Linear Program for Memory Assignment in the DSP Domain G. Grewal, S. Coros, A. Morton (University of Waterloo), and D. Banerji University of Guelph Predicting L2 Misses to Increase Issue-Queue Efficacy Enric Morancho, Jose Maria Llaberia, and Angel Olive Universitat Politecnica de Catalunya
12:00 - 1:00	Lunch
1:00 - 2:30	Session 2: Caching Efficiency
	RACE: A Robust Adaptive Caching Strategy for Buffer Yifeng Zhu and Hong Jiang (University of Nebraska - Lincoln) University of Maine Optimizing Kernel Block Memory Operations Michael Calhoun, Scott Rixer, and Alan Cox Rice University Exploiting Non-Uniform Memory Access Patterns Through Bitline Segmentation Ravishankar Rao, Justin Wenck, Diana Franklin (California Polytechnic State University), Rajeevan Amirtharajah, and Venkatesh Akella University of California Davis A Characterization Study on Memory Value Reuse Lei Jin and Sangyeun Cho University of Pittsburgh
2:30 - 3:30	Poster Session
	Open Nested Transactions: Semantics and Support J. Eliot B. Moss University of Massachusettsi Energy-Aware Microprocessor Synchronization: Transactional Memory vs. Locks Tali Moreshet, R. Iris Bahar, and Maurice Herlihy Brown University Accessing Data on SGI Altix: An Experience with Reality Guido Juckeland, Matthias S. Muller, Wolfgang E. Nagel, and Stefan Pfluger TU Dresden, Center for Information Services and High Performance Computing The Design of Cost-Effective Stride-Prefetching for Modern Processors Hassan Al-Sukhni, James Holt, Daniel A. Connors (Univ. of Colorado), Mike Snyder, Matt Smittle, and Brian Grayson Freescale Semiconductor Inc. On Reducing Load/Store Latencies of Cache Accesses Jia-Jhe Li, and Yuan-Shin Hwang National Taiwan Ocean University
3:30 - 5:00	Session 3: Bus/Memory/Disk Architecture
	A Fast Dynamic Compression Scheme for Low-Latency On-Chip Address Buses Jiangjiang Liu, Krishnan Sundaresan, and Nihar R. Mahapatra (Michigan State University) Lamar University Stream Data Burst Using Embedded Shape Information Sek M. Chai and Abelardo Lopez-Lagunas (ITESM-Toluca, Mexico) Motorola Labs Building a Flexible and Scalable DRAM Interface for Networking Applications on FPGA Jike Chong, Chidamber Kulkarni, and Gordon Brebner (Xilinx Inc) UC, Berkeley An Empirical Evaluation of Semiconductor File Memory as a Disk Cache  John C. Koob, Duncan G. Elliott, and Bruce F. Cockburn University of Alberta

The last 30 minutes of each regular session is reserved for a roundtable-like discussion between all of the presenters and the audience. Come loaded with ideas and questions!