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                               CALL FOR PAPERS
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                 Workshop on Solving the Memory Wall Problem

                     To be held in conjunction with the

                       27th International Symposium on
                       Computer Architecture (ISCA 27)

                               Vancouver, B.C.
                              June 12-14, 2000



Topics:

The goal of this workshop is to provide a forum for researchers and
practitioners from academia and industry to discuss advances in technology,
architecture, and algorithms that address the growing gap between
CPU/network and memory speeds. Both hardware and software approaches to
addressing this speed gap are encouraged.

We are especially interested in attracting new, experimental or paper
techniques, technologies and algorithms that address this issue. Note, we
discourage papers that simply provide yet a new incremental improvement to
cache performance.

Please submit a 10 page extended abstract for review by the program
committee. Authors of accepted abstracts will have an opportunity to present
a 30-minute talk on their work. We hope to encourage presentations of work
in early stages of development. A post-workshop proceedings will be
published.

Possible topics for talks include, but are not limited to:

   * Processors in memory
   * Novel RAM architectures
   * RAM technology issues
   * Intelligent disks
   * Bus architectures
   * Network memory
   * Off-chip interconnect design
   * Compilation techniques
   * Real-time memory compression
   * Operating system memory management
   * Reconfigurable memory systems


The keynote address will be provided by Maurice Wilkes, AT&T Cambridge,
England.


Organizers:

Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu)
David Kaeli, Northeastern University (kaeli@ece.neu.edu)



Program Committee

   * Erik Altman, IBM Research
   * Jean Loup Baer, University of Washington
   * Brad Calder, UC San Diego
   * Tien-Fu Chen, National Chung Cheng University
   * Bruce Cockburn, University of Alberta
   * Duncan Elliot, University of Alberta
   * Michael Foster, NSF
   * Antonio Gonzalez, UPC
   * Mark Johnson, Naval Research Lab
   * Artur Klauser, Compaq
   * Fabrizio Lombardi, Northeastern University
   * Sally McKee, University of Utah
   * Waleed Meleis, Northeastern University
   * Trevor Mudge, University of Michigan
   * Shubu Mukherjee, Compaq
   * Walid Najjar, Colorado St.
   * Laurence Sadwick, University of Utah
   * Andre Seznec, IRISA
   * Per Strenstrom, Chalmers University
   * Gary Tyson, University of Michigan
   * Augustus Uht, University of Rhode Island



Submissions:

Please send your 10 page extended abstract in ps or pdf to either of the
workshop co-chairs by March 15, 2000.



           Haldun Hadimioglu                          David Kaeli
         Polytechnic University                 Northeastern University
        (haldun@photon.poly.edu)                  (kaeli@ece.neu.edu)



Important Dates:

Abstracts due: March 15, 2000
Notification to authors: April 28, 2000
Final papers due: May 26, 2000   * Network memory
   * Off-chip interconnect design
   * Compilation techniques
   * Real-time memory compression
   * Operating system memory management
   * Reconfigurable memory systems


The keynote address will be provided by Maurice Wilkes, AT&T Cambridge,
England.


Organizers:

Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu)
David Kaeli, Northeastern University (kaeli@ece.neu.edu)