Technical Program Schedule

Saturday, February 16th, 2008
7:00AM - 8:00AM Breakfast
All Day Events
8:00AM - 5:00PM		 Tutorial: Architectural Implications of Multiple Clock Domains Multiple Voltage Domains and Dynamic Voltage-Frequency Scaling (MCD/MVD/DVFS)
Workshop: The Twelfth Workshop on Interaction between Compilers and Computer Architectures (Interact-12)
Please enjoy breakfast and morning/afternoon breaks. Lunch and dinner not provided on Saturday.

Sunday, February 17th, 2008
7:00AM - 8:00AM Breakfast
All Day Events
8:00AM - 5:00PM		 Workshop: The Eleventh Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-11)
Workshop: 1st International Workshop on Storage and I/O Virtualization, Performance, Energy, Evaluation and Dependability (SPEED 2008)
Morning Events
8:00AM - 12:00AM		 Tutorial: Power Management Solutions for Computer Systems
Afternoon Events
1:30PM - 5:30PM		 Tutorial: High-Speed Network Architectures for Clusters: Designs and Trends
Workshop on Computer Architecture Research Directions (CARD-2007)     CANCELLED
5:30PM - 6:00PM Break
6:00PM - 8:00PM WELCOME RECEPTION: Hors d'ouerves, drinks, and great company [Olympus Ballroom]
Please enjoy breakfast, breaks, and the reception. Lunch not provided on Sunday.

Monday, February 18th, 2008
7:30AM - 8:30AM Breakfast
8:30AM - 8:50AM Welcome Message
8:50AM - 10:00AM Keynote I
Chair: Antonio Gonzalez, Intel Barcelona Research Center & UPC
Intel’s Tera-scale Computing Project: The First Five Years, the Next Five Years (pdf)
Joe Schutz, Intel Corp.
10:00AM - 10:30AM Break
10:30AM - 12:00PM

INDUSTRIAL SESSION
Chair: Pradeep Dubey, Intel Corp.
Design and Implementation of the Blue Gene/P Snoop Filter (pdf) (slides)
Valentina Salapura, Matthias Blumrich, and Alan Gara (IBM Corporation)

Fabric Convergence Implications on Systems Architecture (pdf) (slides)
Kevin Leigh, Parthasarathy Ranganathan, and Jaspal Subhlok (Hewlett Packard)

Prediction of CPU Idle-Busy Activity Pattern (pdf) (slides)
Qian Diao and Justin J Song (Intel Corporation)
12:00PM - 1:30PM Lunch
1:30PM - 3:30PM

SESSION 1A: PATH AND BRANCH PREDICTION (Parallel session - Capitol A/B)
Chair: Lieven Eeckhout, Ghent University
Performance-Aware Speculation Control Using Wrong Path Usefulness Prediction (pdf) (slides)
Chang Joo Lee, UT-Austin;
Hyesoon Kim, Georgia Institute of Technology;
Onur Mutlu, Microsoft Research;
Yale Patt, UT-Austin;

PaCo: Probability-based Path Confidence Prediction (pdf) (slides)
Kshitiz Malik, University of Illinois at Urbana-Champaign;
Mayank Agarwal, University of Illinois at Urbana-Champaign;
Vikram Dhar, University of Illinois at Urbana-Champaign;
Matthew I. Frank, University of Illinois at Urbana-Champaign;

Branch-mispredict Level Parallelism (BLP) for Proactive Control Independence (pdf) (slides)
Kshitiz Malik, University of Illinois at Urbana-Champaign;
Mayank Agarwal,University of Illinois at Urbana-Champaign;
Sam S. Stone, University of Illinois at Urbana-Champaign;
Kevin M Woley, University of Illinois at Urbana-Champaign;
Matthew I. Frank,University of Illinois at Urbana-Champaign;

Address-Branch Correlation: A Novel Locality for Long-Latency Hard-to-Predict Branches (pdf) (slides)
Hongliang Gao, University of Central Florida;
Yi Ma, University of Central Florida;
Martin Dimitrov, University of Central Florida;
Huiyang Zhou, University of Central Florida;

SESSION 1B: POWER AND THERMAL MANAGEMENT (Parallel session - Capitol C)
Chair: Ahmed Louri, University of Arizona
EXCES: EXternal Caching in Energy Saving Storage Systems (pdf) (slides)
Luis Useche, Florida International University;
Jorge Guerra, FloridaInternational University;
Medha Bhadkamkar, Florida International University;
Mauricio Alarcon, Florida International University;
Raju Rangaswami, Florida International University;

Cluster-level Feedback Power Control for Performance Optimization (pdf) (slides)
Xiaorui Wang, University of Tennessee, Knoxville;
Ming Chen, University of Tennessee, Knoxville;

C-Oracle: Predictive Thermal Management for Data Centers (pdf) (slides)
Luiz Ramos, Rutgers University;
Ricardo Bianchini, Rutgers University;

System Level Analysis of Fast, Per-Core DVFS using On-Chip Switching Regulators (pdf) (slides)
Wonyoung Kim, Harvard University;
Meeta Gupta, Harvard University;
Gu-Yeon Wei, Harvard University;
David Brooks, Harvard University;
3:30PM - 4:00PM Break
4:00PM - 5:00PM

SESSION 2A: SMT (Parallel session - Capitol A/B)
Chair: Uri Weiser, Technion IIT

PEEP: Exploiting Predictability of Memory Dependences in SMT Processors (pdf) (slides)
Samantika Subramaniam, Georgia Institute of technology;
Milos Prvulovic, Georgia Institute of Technology;
Gabriel H. Loh, Georgia Institute of Technology;

Runahead Threads to Improve SMT Performance (pdf) (slides)
Tanausu Ramirez, DAC - UPC;
Alex Pajuelo,DAC - UPC;
Oliverio J. Santana, ULPGC;
Mateo Valero, DAC - UPC;

SESSION 2B: SECURITY (Parallel session - Capitol C)
Chair: David Kaeli, Northeastern University

Single-Level Integrity and Confidentiality Protection for Distributed Shared Memory Multiprocessors (pdf) (slides)
Brian Rogers, North Carolina State University;
Chenyu Yan, Georgia Institute of Technology;
Siddhartha Chhabra, North Carolina State University;
Milos Prvulovic, Georgia Institute of Technology;
Yan Solihin, North Carolina State University;

FlexiTaint: Programmable Architectural Support for Efficient Dynamic Taint Propagation (pdf) (slides)
Guru Venkataramani, Georgia Tech;
Ioannis Doudalis, Georgia Tech;
Yan Solihin, NCSU;
Milos Prvulovic, Georgia Tech;
5:00PM - 5:30PM Break
5:30PM - 7:00PM TCC Business Meeting - Capitol A/B

Tuesday, February 19th, 2008
7:30AM - 9:00AM Breakfast
9:00AM - 10:00AM KEYNOTE SESSION II
Chair: Per Stenstrom, Chalmers University of Technology
Amdahl’s Law in the Multicore Era
Mark D. Hill, University of Wisconsin, Madison
10:00AM - 10:30AM Break
10:30AM - 12:00PM

SESSION 3: NETWORK-ON-CHIP
Chair: Rajeev Balasubramonian, University of Utah

CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect (pdf) (slides)
M Frank Chang,University of California, Los Angeles;
Jason Cong, University of California, Los Angeles;
Adam Kaplan, University of California, Los Angeles;
Mishali Naik, University of California, Los Angeles;
Glenn Reinman, University of California, Los Angeles;
Eran Socher, University of California, Los Angeles;
Sai-Wang Tam,University of California, Los Angeles;

Regional Congestion Awareness for Load Balance in Networks-on-Chip (pdf) (slides)
Paul Gratz, Department of Electrical and Computer Engineering, UT Austin;
Boris Grot,Department of Computer Sciences, UT Austin;
Stephen W. Keckler, Department of Computer Sciences, UT Austin;

Performance and Power Optimization through Data Compression in Network-on-Chip Architectures (pdf) (slides)
Reetuparna Das, Pennsylvania State University;
Asit K. Mishra, Pennsylvania State University;
Chrysostomos Nicopoulus, Pennsylvania State University;
Dongkook Park, Pennsylvania State University;
Vijay Narayanan, Pennsylvania State University;
Ravishankar Iyer, Intel Corporation;
Mazin S. Yousif, Intel Corporation;
Chita R Das, Pennsylvania State University;
12:00PM - 1:30PM Lunch
1:30PM - 3:30PM

SESSION 4: MICROARCHITECTURE MODELING AND ANALYSIS
Chair: Yale N. Patt, University of Texas at Austin
Automated Microprocessor Stressmark Generation (pdf) (slides)
Ajay M. Joshi, University of Texas at Austin;
Lieven Eeckhout, Ghent University, Belgium;
Lizy K. John, University of Texas at Austin;
Ciji Isen, University of Texas at Austin;

Roughness of Microarchitectural Design Topologies and its Implications for Optimization (pdf) (slides)
Benjamin C. Lee, Harvard University;
David M. Brooks, Harvard University;

Fundamental Performance Constraints in Horizontal Fusion of In-order Cores (pdf) (slides)
Pierre Salverda, UIUC;
Craig Zilles, UIUC;

Serializing Instructions in System-Intensive Workloads: Amdahl's Law Strikes Again (pdf) (slides)
Philip M. Wells, University of Wisconsin-Madison;
Gurindar S. Sohi, University of Wisconsin-Madison;
3:30-9:00PM EXCURSION: Utah Olympic Park
 

Wednesday, February 20th, 2008
7:30AM - 8:30AM Breakfast
8:30AM - 9:30AM

SESSION 5A: CODE ANALYSIS AND OPTIMIZATION (Parallel session - Olympus A)
Chair: Stefanos Kaxiras, University of Patras

Thread-Safe Dynamic Binary Translaction using Transactional Memory (pdf) (slides)
JaeWoong Chung, Stanford Univ.;
Michael Dalton, Stanford Univ.;
Hari Kannan, Stanford Univ.;
Christos Kozyrakis,Stanford Univ.;

Uncovering Hidden Loop Level Parallelism in Sequential Applications (pdf) (slides)
Hongtao Zhong, University of Michigan;
Mojtaba Mehrara, University of Michigan;
Steve Lieberman, University of Michigan;
Scott Mahlke, University of Michigan;

SESSION 5B: DRAM (Parallel session - Olympus B)
Chair: Anders Landin, Sun Microsystems Inc.
A Comprehensive Approach to DRAM Power Management (pdf) (slides)
Ibrahim Hur, IBM;
Calvin Lin, The University of Texas at Austin;

Power Efficient DRAM Speculation (pdf) (slides)
Nidhi Aggarwal, UW-Madison;
Jason F Cantin, IBM;
Mikko H Lipasti, UW-Madison;
James E Smith, UW-Madison;
9:30AM - 10:00AM Break
10:00AM - 12:00PM

SESSION 6A: PARALLEL ARCHITECTURES (Parallel session - Olympus A)
Chair: Josep Torrellas, University of Illinois, Urbana Champaign

High-Throughput Pairwise Point Interactions in Anton, a Specialized Machine for Molecular Dynamics Simulation (pdf)
Richard H. Larson, D. E. Shaw Research;
John K. Salmon, D. E. Shaw Research;
Ron O. Dror, D. E. Shaw Research;
Martin M. Deneroff, D. E. Shaw Research;
Cliff Young, D. E. Shaw Research;
John L. Klepeis, D. E. Shaw Research;
David E. Shaw, D. E. Shaw Research and Columbia University;

Incorporating Flexibility in Anton, a Specialized Machine for Molecular Dynamics Simulation (pdf)
Jeffrey S. Kuskin, D. E. Shaw Research;
Cliff Young, D. E. Shaw Research;
J.P. Grossman, D. E. Shaw Research;
Brannon Batson, D. E. Shaw Research;
Martin M. Deneroff, D. E. Shaw Research;
Ron O. Dror, D. E. Shaw Research;
David E. Shaw, D. E. Shaw Research and Columbia University;

An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs (pdf) (slides)
Christian Fensch, University of Edinburgh;
Marcelo Cintra, University of Edinburgh;

Gaining Insights into Multicore Cache Partitioning: Bridging the Gap between Simulation and Real Systems (pdf) (slides)
Jiang Lin, Iowa State University;
Qingda Lu, Ohio State University;
Xiaoning Ding, Ohio State University;
Zhao Zhang, Iowa State University;
Xiaodong Zhang, Ohio State University;
P. Sadayappan, Ohio State University;

SESSION 6B: RELIABILITY AND VALIDATION (Parallel session - Olympus B)
Chair: Xavier Vera, Intel Barcelona Research Center

DeCoR: A Delayed Commit and Rollback Mechanism for Handling Inductive Noise in Microprocessors (pdf) (slides)
Meeta S. Gupta, Harvard University;
Krishna K. Rangan, Harvard University;
Michael D. Smith, Harvard University;
Gu-Yeon Wei, Harvard University;
David M. Brooks, Harvard University

Supporting Highly-Decoupled Thread-Level Redundancy for Parallel Programs (pdf) (slides)
M Wasiur Rashid, University of Rochester;
Michael Huang, University of Rochester;

Speculative Instruction Validation for Performance-Reliability Trade-off (pdf) (slides)
Sumeet Kumar, SUNY Binghamton;
Aneesh Aggarwal, SUNY Binghamton;

Runtime Validation of Memory Ordering Using Constraint Graph Checking (pdf) (slides)
Kaiyu Chen, Princeton University;
Sharad Malik, Princeton University;
Priyadarsan Patra, Intel Corporation
12:30PM-2:00pm

LUNCH AND KEYNOTE SESSION (with PPoPP in Capitol Ballroom)
Compilers and Parallel Computing Systems
Frances Allen, IBM Fellow Emerita, IBM Corp.