Ultra-Low Power Perceptive Architectures for Natural Interfaces

by
Karthik Ramani

Advised by
Al Davis

Future ubiquitous information services will require natural human interfaces such as speech and visual feature recognition. Performing such tasks in real-time is currently impossible on embedded processors since they are orders of magnitude too slow. High performance microprocessors that perform such tasks exceed the energy consumption demands of an embedded system. ASICs provide a solution to this problem, but they incur expensive and lengthy design cycles and are exclusive to one application. An accurate understanding of the perception algorithms is necessary to design an architecture that will deliver the real-time performance requirement at an embedded power budget. In this study, we perform a detailed analysis of common perception algorithms to decompose the problem into a pipeline of processes. Finally, the algorithms are mapped to a novel programmable clustered VLIW architecture that delivers the required performance at a very low power budget.