CMOS VLSI Cell Library Development Project

by
Vamshi Krishna Kadaru

Advised by
Erik Brunvand

Complex VLSI (Very Large Scale Integration) circuits can only be designed through the use of equally complex CAD (Computer Aided Design) tools. A typical integrated circuit design flow uses CAD tools and Standard Cells as the basis for building the circuits. Standard cells are pre-designed circuit pieces that the CAD tools use to assemble larger circuits. It is very important for the standard cells to be properly characterized and documented to achieve accurate results. This project enhances the present CAD tool suite by developing industry-style standard cells for student use. Different views have been constructed for each standard cell to abstract the circuit and make the cells usable by the tools. Each view encapsulates different features of the circuit. All these representations combine to form a complete design.

For the above purpose, we have chosen a suitable set of (25) digital library cells to build. Compared to cell libraries of major companies that contain around 400 cells, there has been evidence that a much smaller library, if carefully chosen can be almost as good. These cells have been characterized in terms of their functionality, timing and electrical behavior. They have also been verified to work with the CAD tools from Cadence and Synopsys. The cells are also being documented and are going to be packaged up to release for use by other universities that would like to use them.