Workshop Scope

The high latency and energy of main memory has been a bottleneck within high performance computer systems for many years. However, increases in IPC due to core microarchitecture advances have been slowing in recent years, putting more attention on the memory subsystem. While logic has become more energy-efficient, the energy per memory operation has increased because of higher link speeds and the use of buffer chips. In addition to the growing memory bottleneck, new memory technologies are emerging to challenge the traditional dominance of DRAM. DRAM itself has also been evolving, through the development of 3DS, HBM, HMC, and Wide IO. All of these factors demand novel memory architectures and organizations, methods of scheduling and managing memory, and algorithms for maintaining reliable data storage with unreliable bits. Indeed, there has been an explosion in memory papers since 2009. The Memory Forum will bring together researchers from both academia and industry to discuss advances in memory architecture, organization, and management. The workshop will include a few invited talks to educate the audience about upcoming technologies. The rest of the program will include short presentations based on submitted papers -- the goal is to provide feedback to authors on early-stage and exciting ideas.

The Memory Forum 2014 will be held in conjunction with the 41st International Symposium on Computer Architecture (ISCA-41) , Saturday, June 14th 2014 in Minneapolis, Minnesota.