Colloquium
Uri Weiser
Technion IIT
Monday, August 13, 2012
3147 MEB
Refreshments 3:20p.m.
Lecture 3:40 p.m.
Title: Microarchitecture next Steps? Multitasking and Heterogeneous Computing
Uri Weiser
Technion IIT
Monday, August 13, 2012
3147 MEB
Refreshments 3:20p.m.
Lecture 3:40 p.m.
Title: Microarchitecture next Steps? Multitasking and Heterogeneous Computing
Abstract
For decades computing industry trends have been driven by Moore's "Law". Some elements of this trend are changing while power and energy consumption become limiting factors. The shift to Multicore is only an intermediate solution; much greater changes are needed to continue the computing performance trend. Current process technology drives the industry to on-die Heterogeneous computing. One of the many questions to ask is: what should be the optimal resource sharing of such die? The presentation will present two simple analytical models that enable to reach optimal solutions. The first model will lead to a solution in a symmetric CMP domain. A simplified conceptual models of the two systems (Cache based system and MT system) will be presented, together with a study of their performance and power requirements. The analysis identifies operation zones (based on number of threads running) for which each architecture is more suitable. Moreover, it shows that there is an intermediate "performance valley" between the two, in which both architectures deliver inferior performance. We will show a dynamic optimal solution to prevent this performance drop. The second model will lead to an optimal resource sharing in Heterogeneous systems. When introducing different performance enhancement features the first question to be asked is what is the optimal resource (e.g. power, energy, area, IO) sharing should we choose? We will present an analytical model that will enable to identify such optimal solution.
BIO
Dr. Uri Weiser is a visiting Professor at the Electrical Engineering department, the Technion IIT and is in the advisory board of numerous startups. He received the bachelor and master degrees in EE from the Technion and Ph.D in CS from the University of Utah, Salt Lake City. Uri worked at Intel from 1988-2006. At Intel, Uri initiated the definition of the Pentium® processor, drove the definition of Intel's MMX™ technology, co-invented the Trace Cache, co-managed the new Intel Microprocessor Design Center at Austin, Texas and initiated an Advanced Media applications research activity. Uri was appointed as Intel Fellow in 1996, in 2002 he became an IEEE Fellow and in 2005 an ACM Fellow. Prior to his career at Intel, Uri worked for the Israeli Department of Defense as a research and system engineer and later at National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor. Uri was an Associate Editor of IEEEMicro Magazine (1992-2004) and is Associate Editor of Computer Architecture Letters.
For decades computing industry trends have been driven by Moore's "Law". Some elements of this trend are changing while power and energy consumption become limiting factors. The shift to Multicore is only an intermediate solution; much greater changes are needed to continue the computing performance trend. Current process technology drives the industry to on-die Heterogeneous computing. One of the many questions to ask is: what should be the optimal resource sharing of such die? The presentation will present two simple analytical models that enable to reach optimal solutions. The first model will lead to a solution in a symmetric CMP domain. A simplified conceptual models of the two systems (Cache based system and MT system) will be presented, together with a study of their performance and power requirements. The analysis identifies operation zones (based on number of threads running) for which each architecture is more suitable. Moreover, it shows that there is an intermediate "performance valley" between the two, in which both architectures deliver inferior performance. We will show a dynamic optimal solution to prevent this performance drop. The second model will lead to an optimal resource sharing in Heterogeneous systems. When introducing different performance enhancement features the first question to be asked is what is the optimal resource (e.g. power, energy, area, IO) sharing should we choose? We will present an analytical model that will enable to identify such optimal solution.
BIO
Dr. Uri Weiser is a visiting Professor at the Electrical Engineering department, the Technion IIT and is in the advisory board of numerous startups. He received the bachelor and master degrees in EE from the Technion and Ph.D in CS from the University of Utah, Salt Lake City. Uri worked at Intel from 1988-2006. At Intel, Uri initiated the definition of the Pentium® processor, drove the definition of Intel's MMX™ technology, co-invented the Trace Cache, co-managed the new Intel Microprocessor Design Center at Austin, Texas and initiated an Advanced Media applications research activity. Uri was appointed as Intel Fellow in 1996, in 2002 he became an IEEE Fellow and in 2005 an ACM Fellow. Prior to his career at Intel, Uri worked for the Israeli Department of Defense as a research and system engineer and later at National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor. Uri was an Associate Editor of IEEEMicro Magazine (1992-2004) and is Associate Editor of Computer Architecture Letters.